---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 12/02/2016 12:48:56 PM -- Design Name: -- Module Name: countdown - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity timerclock is Port ( Clk, start : in STD_LOGIC; state : in STD_LOGIC_VECTOR (2 downto 0); current : out STD_LOGIC_VECTOR (7 downto 0); timeout : out STD_LOGIC); end timerclock; architecture Behavioral of timerclock is component clockdivider port ( ClkIn : in STD_LOGIC; divisor : in STD_LOGIC_VECTOR (31 downto 0); ClkOut : out STD_LOGIC); end component; signal timer1s : STD_LOGIC := '0'; signal timer10s : STD_LOGIC := '0'; signal t1, t10 : STD_LOGIC := '0'; begin clock_1s : clockdivider port map ( ClkIn => CLK , divisor => X"02FAF080" , ClkOut => timer1s); -- 1s clock period process (timer10s) is variable timeleft : unsigned (3 downto 0) := "0000"; -- initialize and set 10s place to 5 variable timer10s : unsigned (3 downto 0) := "0000"; -- clock for the 10s begin if (start = '1') then -- if start is pressed timeleft := "0000"; -- set the time to 0 timer10s := "0000"; -- 10s place timer = 0 else if ( rising_edge(timer1s)) then -- if 1s has passed if timer10s = "1001" then -- if 10s timer is 9 timer10s := "0000"; -- 10s timer is set to 0 timeleft := timeleft + 1; -- count up very 10 s else timer10s := timer10s + 1; -- count to 9 timeleft := timeleft; -- 10s place time remains the same end if; if ( timeleft = "0110") then -- if 10s place time is 6 t10 <= '1'; else t10 <= '0'; end if; end if; end if; current (7 downto 4) <= STD_LOGIC_VECTOR(timeleft); end process; process (timer1s) is variable timeright : unsigned (3 downto 0) := "0000"; -- initialize and set 1s place to 0 begin if (start = '1') then -- if start is pressed timeright := "0000"; -- set to 0 at the start else if ( rising_edge(timer1s)) then if (timeright = "1001") then -- if 1s place is 9 timeright := "0000"; -- set to 0 t1 <= '1'; else timeright := timeright + 1; -- count up very 1 s t1 <= '0'; end if; end if; end if; current (3 downto 0) <= STD_LOGIC_VECTOR(timeright); end process; timeout <= t1 and t10; -- if 10s place is 6 and 1s place is 0 then time is out end Behavioral;