library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity counter_new is Port ( CLK : in STD_LOGIC; RST : in STD_LOGIC; COUNT : out STD_LOGIC_VECTOR (7 downto 0)); end counter_new; architecture Behavioral of counter_new is signal t_count : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); begin process (CLK, RST) begin if (RST = '0') then t_count <= x"00"; elsif (rising_edge(CLK)) then t_count <= t_count + 1; end if; end process; COUNT <= t_count; end Behavioral;