D_FlipFlop Project Status (12/03/2014 - 06:32:05)
Project File: TicTacToe_V2.xise Parser Errors: No Errors
Module Name: D_FlipFlop Implementation State: Programming File Not Generated
Target Device: xc3s500e-4fg320
  • Errors:
  
Product Version:ISE 14.7
  • Warnings:
  
Design Goal: Balanced
  • Routing Results:
  
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
  
Environment:  
  • Final Timing Score:
   
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentWed Dec 3 06:32:01 2014
WebTalk Log FileCurrentWed Dec 3 06:32:04 2014

Date Generated: 12/03/2014 - 06:32:05