Main_Game_Board Project Status (12/12/2014 - 00:19:47)
Project File: TicTacToe_V2.xise Parser Errors: No Errors
Module Name: Main_Game_Board Implementation State: Programming File Generated
Target Device: xc3s500e-4fg320
  • Errors:
No Errors
Product Version:ISE 14.5
  • Warnings:
26 Warnings (15 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 45 9,312 1%  
Number of 4 input LUTs 30 9,312 1%  
Number of occupied Slices 48 4,656 1%  
    Number of Slices containing only related logic 48 48 100%  
    Number of Slices containing unrelated logic 0 48 0%  
Total Number of 4 input LUTs 30 9,312 1%  
Number of bonded IOBs 43 232 18%  
Number of BUFGMUXs 1 24 4%  
Average Fanout of Non-Clock Nets 2.96      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentFri Dec 12 00:19:05 2014026 Warnings (15 new)3 Infos (0 new)
Translation ReportCurrentFri Dec 12 00:19:12 2014000
Map ReportCurrentFri Dec 12 00:19:20 2014002 Infos (0 new)
Place and Route ReportCurrentFri Dec 12 00:19:32 2014002 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentFri Dec 12 00:19:35 2014006 Infos (0 new)
Bitgen ReportCurrentFri Dec 12 00:19:40 2014000
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateWed Dec 3 06:50:52 2014
WebTalk ReportCurrentFri Dec 12 00:19:40 2014
WebTalk Log FileCurrentFri Dec 12 00:19:47 2014

Date Generated: 12/12/2014 - 00:19:47