---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 03/08/2018 10:26:29 AM -- Design Name: -- Module Name: Master_Final_Project - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Master_Final_Project is Port ( BTN : in STD_LOGIC; CLK : in STD_LOGIC; MS : in STD_LOGIC_VECTOR (3 downto 0); LED : out STD_LOGIC_VECTOR (15 downto 0)); end Master_Final_Project; architecture Behavioral of Master_Final_Project is component final_project is Port ( --CLK : in STD_LOGIC; NMS : in STD_LOGIC_VECTOR (3 downto 0); BTN : in STD_LOGIC; --sw : in STD_LOGIC_Vector (1 downto 0); LED : out STD_LOGIC_VECTOR (15 downto 0)); end component; component Final_DFF is Port ( CLK : in STD_LOGIC; D : in STD_LOGIC_Vector (3 downto 0); Q : out STD_LOGIC_Vector (3 downto 0)); end component; component Final_DFF2 is Port ( CLK : in STD_LOGIC; BTN : in STD_LOGIC; Q : out STD_LOGIC); end component; signal DFF02proj30 : STD_LOGIC; signal DFF12proj74 : STD_LOGIC; signal DFF22proj118 : STD_LOGIC; signal DFF32proj1512 : STD_LOGIC; signal DFFBTN2proj : STD_LOGIC; begin DFF0: Final_DFF port map ( CLK => CLK, D(0) => MS(0), D(1) => MS(1), D(2) => MS(2), D(3) => MS(3), Q(0) => DFF02proj30, Q(1) => DFF12proj74, Q(2) => DFF22proj118, Q(3) => DFF32proj1512); DFF1: Final_DFF2 port map ( CLK => CLK, BTN => BTN, Q => DFFBTN2proj); Proj0: final_project port map ( NMS(0) => DFF02proj30, NMS(1) => DFF12proj74, NMS(2) => DFF22proj118, NMS(3) => DFF32proj1512, BTN => DFFBTN2proj, LED => LED); end Behavioral;