---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 12/04/2016 05:49:58 PM -- Design Name: -- Module Name: Master - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Master is Port ( sensor : in STD_LOGIC_VECTOR (9 downto 0); switch : in STD_LOGIC_VECTOR (6 downto 0); button : in STD_LOGIC; output : out STD_LOGIC; CLK : in STD_LOGIC; DISP_EN : out STD_LOGIC_VECTOR (3 downto 0); SEGMENTS : out STD_LOGIC_VECTOR (7 downto 0)); end Master; architecture Behavioral of Master is component FSM is Port ( UI : in STD_LOGIC_VECTOR (6 downto 0); S : in STD_LOGIC_VECTOR (6 downto 0); O : out STD_LOGIC); end component FSM; component mult is Port ( sensor : in STD_LOGIC_VECTOR (9 downto 0); percent : out STD_LOGIC_VECTOR (6 downto 0); CLK : in STD_LOGIC); end component mult; component sseg_dec is Port ( ALU_VAL : in std_logic_vector(7 downto 0); SIGN : in std_logic; VALID : in std_logic; CLK : in std_logic; DISP_EN : out std_logic_vector(3 downto 0); SEGMENTS : out std_logic_vector(7 downto 0)); end component sseg_dec; component flipflops is Port ( SWITCHES : in std_logic_vector(6 downto 0); clk : in std_logic; BTN : in std_logic; LEVEL : out std_logic_vector(6 downto 0)); end component flipflops; signal sseg_sig: std_logic_vector ( 7 downto 0); signal sig1, sig2: std_logic_vector ( 6 downto 0); begin comparator: FSM Port map (UI => switch, S => sig1, O => output); mult1: mult Port Map (sensor => sensor, percent => sig1, CLK => CLK); sseg_sig <= '0' & sig1; display: SSEG_dec Port map( ALU_VAL => sseg_sig, SIGN => '0', VALID => '1', CLK => CLK, DISP_EN => DISP_EN, SEGMENTS => SEGMENTS); FF: flipflops Port map( SWITCHES => switch, clk => clk, BTN => button, LEVEL => sig2); end Behavioral;