-------------------------------------------------------------------------------- -- Company: Cal Poly SLO -- Engineer: Neal Nguyen & Bryan Bellin -- -- Create Date: 19:33:20 11/27/2014 -- Design Name: Score decoder test simulation file -- Module Name: score_dec_test.vhd -- Project Name: FinalProject1 -- Target Device: Nexys 3 -- VHDL Test Bench Created by ISE for module: score_dec -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY score_dec_test IS END score_dec_test; ARCHITECTURE behavior OF score_dec_test IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT score_dec PORT( CLK : IN std_logic; reset_n : IN std_logic; Score : OUT std_logic_vector(7 downto 0) ); END COMPONENT; --Inputs signal CLK : std_logic := '0'; signal reset_n : std_logic := '0'; --Outputs signal Score : std_logic_vector(7 downto 0); -- Clock period definitions constant CLK_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: score_dec PORT MAP ( CLK => CLK, reset_n => reset_n, Score => Score ); -- Clock process definitions CLK_process :process begin CLK <= '0'; wait for CLK_period/2; CLK <= '1'; wait for CLK_period/2; end process; -- Stimulus process stim_proc: process begin -- hold reset state for 100 ns. wait for 100 ns; wait for CLK_period*10; -- insert stimulus here reset_n <= '1'; wait for 1000 ns; reset_n <= '0'; wait for 1000 ns; wait; end process; END;