# File saved with Nlview 6.8.5 2018-01-30 bk=1.4354 VDI=40 GEI=35 GUI=JA:1.6 non-TLS-threadsafe # # non-default properties - (restore without -noprops) property attrcolor #000000 property attrfontsize 8 property autobundle 1 property backgroundcolor #ffffff property boxcolor0 #000000 property boxcolor1 #000000 property boxcolor2 #000000 property boxinstcolor #000000 property boxpincolor #000000 property buscolor #008000 property closeenough 5 property createnetattrdsp 2048 property decorate 1 property elidetext 40 property fillcolor1 #ffffcc property fillcolor2 #dfebf8 property fillcolor3 #f0f0f0 property gatecellname 2 property instattrmax 30 property instdrag 15 property instorder 1 property marksize 12 property maxfontsize 12 property maxzoom 5 property netcolor #19b400 property objecthighlight0 #ff00ff property objecthighlight1 #ffff00 property objecthighlight2 #00ff00 property objecthighlight3 #ff6666 property objecthighlight4 #0000ff property objecthighlight5 #ffc800 property objecthighlight7 #00ffff property objecthighlight8 #ff00ff property objecthighlight9 #ccccff property objecthighlight10 #0ead00 property objecthighlight11 #cefc00 property objecthighlight12 #9e2dbe property objecthighlight13 #ba6a29 property objecthighlight14 #fc0188 property objecthighlight15 #02f990 property objecthighlight16 #f1b0fb property objecthighlight17 #fec004 property objecthighlight18 #149bff property objecthighlight19 #eb591b property overlapcolor #19b400 property pbuscolor #000000 property pbusnamecolor #000000 property pinattrmax 20 property pinorder 2 property pinpermute 0 property portcolor #000000 property portnamecolor #000000 property ripindexfontsize 8 property rippercolor #000000 property rubberbandcolor #000000 property rubberbandfontsize 12 property selectattr 0 property selectionappearance 2 property selectioncolor #0000ff property sheetheight 44 property sheetwidth 68 property showmarks 1 property shownetname 0 property showpagenumbers 1 property showripindex 4 property timelimit 1 # module new pwm work:pwm:NOFILE -nosplit load symbol RTL_ADD work RTL(+) pin I1 input.left pinBus I0 input.left [8:0] pinBus O output.right [8:0] fillcolor 1 load symbol RTL_MUX5 work MUX pinBus I0 input.left [8:0] pinBus I1 input.left [8:0] pinBus O output.right [8:0] pinBus S input.bot [8:0] fillcolor 1 load symbol RTL_ROM work GEN pin O output.right pinBus A input.left [8:0] fillcolor 1 load symbol RTL_MUX work MUX pin S input.bot pinBus I0 input.left [7:0] pinBus I1 input.left [7:0] pinBus O output.right [7:0] fillcolor 1 load symbol RTL_MUX3 work MUX pin I0 input.left pin I1 input.left pin O output.right pin S input.bot fillcolor 1 load symbol RTL_RSHIFT0 work RTL(>>) pin I1 input.left pin I2 input.left pinBus I0 input.left [30:0] pinBus O output.right [7:0] fillcolor 1 load symbol RTL_MINUS2 work RTL(-) pinBus I0 input.left [7:0] pinBus O output.right [7:0] fillcolor 1 load symbol RTL_EQ work RTL(=) pin I0 input.left pin I1 input.left pin O output.right fillcolor 1 load symbol RTL_MUX1 work MUX pin S input.bot pinBus I0 input.left [30:0] pinBus I1 input.left [30:0] pinBus O output.right [30:0] fillcolor 1 load symbol RTL_LT0 work RTL(<) pin O output.right pinBus I0 input.left [31:0] pinBus I1 input.left [31:0] fillcolor 1 load symbol RTL_MUX0 work MUX pin S input.bot pinBus I0 input.left [30:0] pinBus I1 input.left [31:0] pinBus O output.right [31:0] fillcolor 1 load symbol RTL_MINUS work RTL(-) pinBus I0 input.left [30:0] pinBus O output.right [30:0] fillcolor 1 load symbol RTL_RSHIFT work RTL(>>) pin I2 input.left pinBus I0 input.left [30:0] pinBus I1 input.left [3:0] pinBus O output.right [30:0] fillcolor 1 load symbol RTL_MINUS0 work RTL(-) pinBus I0 input.left [30:0] pinBus O output.right [31:0] fillcolor 1 load symbol RTL_GEQ work RTL(>=) pin O output.right pinBus I0 input.left [31:0] pinBus I1 input.left [31:0] fillcolor 1 load symbol RTL_MULT work RTL(*) pinBus I0 input.left [8:0] pinBus I1 input.left [9:0] pinBus O output.right [18:0] fillcolor 1 load symbol RTL_REG_ASYNC__BREG_4 work GEN pin C input.clk.left pin CE input.left pin CLR input.top pin D input.left pin Q output.right fillcolor 1 load symbol RTL_EQ1 work RTL(=) pin O output.right pinBus I0 input.left [31:0] pinBus I1 input.left [31:0] fillcolor 1 load symbol RTL_SUB work RTL(-) pinBus I0 input.left [31:0] pinBus I1 input.left [7:0] pinBus O output.right [9:0] fillcolor 1 load symbol RTL_EQ0 work RTL(=) pin O output.right pinBus I0 input.left [8:0] pinBus I1 input.left [8:0] fillcolor 1 load symbol RTL_REG_ASYNC__BREG_1 work[8:0]ssww GEN pin C input.clk.left pin CLR input.top pinBus D input.left [8:0] pinBus Q output.right [8:0] fillcolor 1 sandwich 3 prop @bundle 9 load symbol RTL_REG__BREG_2 work[7:0]ssww GEN pin C input.clk.left pin CE input.left pinBus D input.left [7:0] pinBus Q output.right [7:0] fillcolor 1 sandwich 3 prop @bundle 8 load port ena input -pg 1 -y 270 load port reset_n input -pg 1 -y 610 load port clk input -pg 1 -y 190 load portBus duty input [7:0] -attr @name duty[7:0] -pg 1 -y 390 load portBus pwm_n_out output [0:0] -attr @name pwm_n_out[0:0] -pg 1 -y 200 load portBus pwm_out output [0:0] -attr @name pwm_out[0:0] -pg 1 -y 340 load inst half_duty[0]_i RTL_ROM work -attr @cell(#000000) RTL_ROM -pinBusAttr A @name A[8:0] -pg 1 -lvl 11 -y 70 load inst half_duty_new4_i__0 RTL_MINUS0 work -attr @cell(#000000) RTL_MINUS -pinBusAttr I0 @name I0[30:0] -pinBusAttr O @name O[31:0] -pg 1 -lvl 5 -y 320 load inst pwm_n_out_reg[0] RTL_REG_ASYNC__BREG_4 work -attr @cell(#000000) RTL_REG_ASYNC -pg 1 -lvl 17 -y 200 load inst pwm_out1_i RTL_SUB work -attr @cell(#000000) RTL_SUB -pinBusAttr I0 @name I0[31:0] -pinBusAttr I0 @attr V=X\"000001F4\" -pinBusAttr I1 @name I1[7:0] -pinBusAttr O @name O[9:0] -pg 1 -lvl 14 -y 430 load inst half_duty_new4_i__1 RTL_GEQ work -attr @cell(#000000) RTL_GEQ -pinBusAttr I0 @name I0[31:0] -pinBusAttr I1 @name I1[31:0] -pg 1 -lvl 7 -y 540 load inst count_reg[0][8:0] RTL_REG_ASYNC__BREG_1 work[8:0]ssww -attr @cell(#000000) RTL_REG_ASYNC -pg 1 -lvl 10 -y 200 load inst half_duty_new_reg[7:0] RTL_REG__BREG_2 work[7:0]ssww -attr @cell(#000000) RTL_REG -pg 1 -lvl 12 -y 330 load inst half_duty_new2_i RTL_EQ work -attr @cell(#000000) RTL_EQ -pg 1 -lvl 9 -y 620 load inst half_duty_new3_i RTL_MUX0 work -attr @cell(#000000) RTL_MUX -pinBusAttr I0 @name I0[30:0] -pinBusAttr I0 @attr S=1'b0 -pinBusAttr I1 @name I1[31:0] -pinBusAttr I1 @attr S=default -pinBusAttr O @name O[31:0] -pg 1 -lvl 6 -y 370 load inst half_duty_new4_i RTL_RSHIFT work -attr @cell(#000000) RTL_RSHIFT -pinBusAttr I0 @name I0[30:0] -pinBusAttr I1 @name I1[3:0] -pinBusAttr I1 @attr V=B\"1000\" -pinBusAttr O @name O[30:0] -pg 1 -lvl 4 -y 350 load inst pwm_out_reg[0] RTL_REG_ASYNC__BREG_4 work -attr @cell(#000000) RTL_REG_ASYNC -pg 1 -lvl 17 -y 340 load inst half_duty_new5_i__0 RTL_LT0 work -attr @cell(#000000) RTL_LT -pinBusAttr I0 @name I0[31:0] -pinBusAttr I1 @name I1[31:0] -pg 1 -lvl 5 -y 430 load inst pwm_out1_i__0 RTL_EQ0 work -attr @cell(#000000) RTL_EQ -pinBusAttr I0 @name I0[8:0] -pinBusAttr I1 @name I1[8:0] -pg 1 -lvl 15 -y 410 load inst count[0]_i RTL_MUX5 work -attr @cell(#000000) RTL_MUX -pinBusAttr I0 @name I0[8:0] -pinBusAttr I0 @attr S=9'b111110011 -pinBusAttr I1 @name I1[8:0] -pinBusAttr I1 @attr S=default -pinBusAttr O @name O[8:0] -pinBusAttr S @name S[8:0] -pg 1 -lvl 9 -y 60 load inst half_duty_new0_i__0 RTL_MUX3 work -attr @cell(#000000) RTL_MUX -pinAttr I0 @attr S=1'b0 -pinAttr I1 @attr S=default -pg 1 -lvl 11 -y 170 load inst pwm_n_out_i RTL_MUX3 work -attr @cell(#000000) RTL_MUX -pinAttr I0 @attr S=1'b1 -pinAttr I1 @attr S=default -pg 1 -lvl 16 -y 200 load inst pwm_out_i RTL_MUX3 work -attr @cell(#000000) RTL_MUX -pinAttr I0 @attr S=1'b1 -pinAttr I1 @attr S=default -pg 1 -lvl 16 -y 320 load inst half_duty_reg[0][7:0] RTL_REG__BREG_2 work[7:0]ssww -attr @cell(#000000) RTL_REG -pg 1 -lvl 13 -y 430 load inst half_duty_new0_i RTL_MUX work -attr @cell(#000000) RTL_MUX -pinBusAttr I0 @name I0[7:0] -pinBusAttr I0 @attr S=1'b0 -pinBusAttr I1 @name I1[7:0] -pinBusAttr I1 @attr S=default -pinBusAttr O @name O[7:0] -pg 1 -lvl 11 -y 320 load inst half_duty_new6_i RTL_MULT work -attr @cell(#000000) RTL_MULT -pinBusAttr I0 @name I0[8:0] -pinBusAttr I1 @name I1[9:0] -pinBusAttr I1 @attr V=B\"0111110100\" -pinBusAttr O @name O[18:0] -pg 1 -lvl 1 -y 400 load inst count[0]0_i RTL_ADD work -attr @cell(#000000) RTL_ADD -pinBusAttr I0 @name I0[8:0] -pinBusAttr O @name O[8:0] -pg 1 -lvl 8 -y 70 load inst half_duty_new3_i__0 RTL_MINUS work -attr @cell(#000000) RTL_MINUS -pinBusAttr I0 @name I0[30:0] -pinBusAttr O @name O[30:0] -pg 1 -lvl 7 -y 440 load inst half_duty_new5_i RTL_MUX1 work -attr @cell(#000000) RTL_MUX -pinBusAttr I0 @name I0[30:0] -pinBusAttr I0 @attr S=1'b1 -pinBusAttr I1 @name I1[30:0] -pinBusAttr I1 @attr S=default -pinBusAttr O @name O[30:0] -pg 1 -lvl 3 -y 480 load inst pwm_out0_i RTL_EQ1 work -attr @cell(#000000) RTL_EQ -pinBusAttr I0 @name I0[31:0] -pinBusAttr I1 @name I1[31:0] -pg 1 -lvl 15 -y 500 load inst half_duty_new1_i__0 RTL_MINUS2 work -attr @cell(#000000) RTL_MINUS -pinBusAttr I0 @name I0[7:0] -pinBusAttr O @name O[7:0] -pg 1 -lvl 10 -y 360 load inst half_duty_new2_i__0 RTL_MUX1 work -attr @cell(#000000) RTL_MUX -pinBusAttr I0 @name I0[30:0] -pinBusAttr I0 @attr S=1'b1 -pinBusAttr I1 @name I1[30:0] -pinBusAttr I1 @attr S=default -pinBusAttr O @name O[30:0] -pg 1 -lvl 8 -y 500 load inst half_duty_new6_i__0 RTL_MINUS work -attr @cell(#000000) RTL_MINUS -pinBusAttr I0 @name I0[30:0] -pinBusAttr O @name O[30:0] -pg 1 -lvl 2 -y 450 load inst half_duty_new7_i RTL_GEQ work -attr @cell(#000000) RTL_GEQ -pinBusAttr I0 @name I0[31:0] -pinBusAttr I1 @name I1[31:0] -pg 1 -lvl 2 -y 540 load inst half_duty_reg[0]0_i RTL_MUX3 work -attr @cell(#000000) RTL_MUX -pinAttr I0 @attr S=1'b0 -pinAttr I1 @attr S=default -pg 1 -lvl 12 -y 80 load inst pwm_out_i__0 RTL_MUX3 work -attr @cell(#000000) RTL_MUX -pinAttr I0 @attr S=1'b1 -pinAttr I1 @attr S=default -pg 1 -lvl 16 -y 490 load inst half_duty_new1_i RTL_RSHIFT0 work -attr @cell(#000000) RTL_RSHIFT -pinBusAttr I0 @name I0[30:0] -pinBusAttr O @name O[7:0] -pg 1 -lvl 9 -y 390 load inst half_duty_new2_i__1 RTL_LT0 work -attr @cell(#000000) RTL_LT -pinBusAttr I0 @name I0[31:0] -pinBusAttr I1 @name I1[31:0] -pg 1 -lvl 10 -y 450 load net half_duty_new2[15] -attr @rip O[15] -pin half_duty_new1_i I0[15] -pin half_duty_new2_i__0 O[15] load net half_duty_new2[5] -attr @rip O[5] -pin half_duty_new1_i I0[5] -pin half_duty_new2_i__0 O[5] load net half_duty_new3[26] -attr @rip O[26] -pin half_duty_new2_i__0 I1[26] -pin half_duty_new3_i__0 O[26] load net count_reg[0]__0[2] -attr @rip 2 -pin count[0]0_i I0[2] -pin count[0]_i S[2] -pin count_reg[0][8:0] Q[2] -pin half_duty[0]_i A[2] -pin pwm_out0_i I0[2] -pin pwm_out1_i__0 I0[2] load net p_0_in[9] -attr @rip O[9] -pin half_duty_new2_i__0 I0[9] -pin half_duty_new2_i__1 I0[9] -pin half_duty_new3_i O[9] -pin half_duty_new3_i__0 I0[9] -pin half_duty_new4_i__1 I0[9] load net pwm_out_i__0_n_0 -pin pwm_out_i__0 O -pin pwm_out_reg[0] CE netloc pwm_out_i__0_n_0 1 16 1 4800 load net duty[0] -attr @rip duty[0] -port duty[0] -pin half_duty_new6_i I0[0] load net half_duty_new4[22] -attr @rip O[22] -pin half_duty_new3_i I1[22] -pin half_duty_new4_i__0 O[22] load net half_duty_reg[0]__0[2] -attr @rip 2 -pin half_duty_reg[0][7:0] Q[2] -pin pwm_out1_i I1[2] -pin pwm_out1_i__0 I1[2] load net pwm_n_out[0] -attr @rip 0 -port pwm_n_out[0] -pin pwm_n_out_reg[0] Q netloc pwm_n_out[0] 1 17 1 NJ load net half_duty_new3[30] -attr @rip O[30] -pin half_duty_new2_i__0 I1[30] -pin half_duty_new3_i__0 O[30] load net half_duty_new5[7] -attr @rip O[7] -pin half_duty_new4_i I0[7] -pin half_duty_new5_i O[7] load net half_duty_new3[12] -attr @rip O[12] -pin half_duty_new2_i__0 I1[12] -pin half_duty_new3_i__0 O[12] load net count[0][1] -attr @rip O[1] -pin count[0]_i O[1] -pin count_reg[0][8:0] D[1] load net half_duty_new5[25] -attr @rip O[25] -pin half_duty_new4_i I0[25] -pin half_duty_new5_i O[25] load net half_duty_new2[1] -attr @rip O[1] -pin half_duty_new1_i I0[1] -pin half_duty_new2_i__0 O[1] load net half_duty_new6_i__0_n_30 -attr @rip O[0] -pin half_duty_new5_i I1[0] -pin half_duty_new6_i__0 O[0] load net p_0_in[30] -attr @rip O[30] -pin half_duty_new2_i__0 I0[30] -pin half_duty_new2_i__1 I0[30] -pin half_duty_new3_i O[30] -pin half_duty_new3_i__0 I0[30] -pin half_duty_new4_i__1 I0[30] load net p_0_in[19] -attr @rip O[19] -pin half_duty_new2_i__0 I0[19] -pin half_duty_new2_i__1 I0[19] -pin half_duty_new3_i O[19] -pin half_duty_new3_i__0 I0[19] -pin half_duty_new4_i__1 I0[19] load net pwm_n_out_i_n_0 -pin pwm_n_out_i O -pin pwm_n_out_reg[0] CE netloc pwm_n_out_i_n_0 1 16 1 N load net pwm_out[0] -attr @rip 0 -port pwm_out[0] -pin pwm_out_reg[0] Q netloc pwm_out[0] 1 17 1 NJ load net half_duty_new1[6] -attr @rip O[6] -pin half_duty_new0_i I1[6] -pin half_duty_new1_i__0 O[6] load net half_duty_new4_i_n_30 -attr @rip O[0] -pin half_duty_new3_i I0[0] -pin half_duty_new4_i O[0] -pin half_duty_new4_i__0 I0[0] load net half_duty_new6[18] -attr @rip O[18] -pin half_duty_new5_i I0[30] -pin half_duty_new5_i I0[29] -pin half_duty_new5_i I0[28] -pin half_duty_new5_i I0[27] -pin half_duty_new5_i I0[26] -pin half_duty_new5_i I0[25] -pin half_duty_new5_i I0[24] -pin half_duty_new5_i I0[23] -pin half_duty_new5_i I0[22] -pin half_duty_new5_i I0[21] -pin half_duty_new5_i I0[20] -pin half_duty_new5_i I0[19] -pin half_duty_new5_i I0[18] -pin half_duty_new5_i__0 I0[31] -pin half_duty_new5_i__0 I0[30] -pin half_duty_new5_i__0 I0[29] -pin half_duty_new5_i__0 I0[28] -pin half_duty_new5_i__0 I0[27] -pin half_duty_new5_i__0 I0[26] -pin half_duty_new5_i__0 I0[25] -pin half_duty_new5_i__0 I0[24] -pin half_duty_new5_i__0 I0[23] -pin half_duty_new5_i__0 I0[22] -pin half_duty_new5_i__0 I0[21] -pin half_duty_new5_i__0 I0[20] -pin half_duty_new5_i__0 I0[19] -pin half_duty_new5_i__0 I0[18] -pin half_duty_new6_i O[18] -pin half_duty_new6_i__0 I0[30] -pin half_duty_new6_i__0 I0[29] -pin half_duty_new6_i__0 I0[28] -pin half_duty_new6_i__0 I0[27] -pin half_duty_new6_i__0 I0[26] -pin half_duty_new6_i__0 I0[25] -pin half_duty_new6_i__0 I0[24] -pin half_duty_new6_i__0 I0[23] -pin half_duty_new6_i__0 I0[22] -pin half_duty_new6_i__0 I0[21] -pin half_duty_new6_i__0 I0[20] -pin half_duty_new6_i__0 I0[19] -pin half_duty_new6_i__0 I0[18] -pin half_duty_new7_i I0[31] -pin half_duty_new7_i I0[30] -pin half_duty_new7_i I0[29] -pin half_duty_new7_i I0[28] -pin half_duty_new7_i I0[27] -pin half_duty_new7_i I0[26] -pin half_duty_new7_i I0[25] -pin half_duty_new7_i I0[24] -pin half_duty_new7_i I0[23] -pin half_duty_new7_i I0[22] -pin half_duty_new7_i I0[21] -pin half_duty_new7_i I0[20] -pin half_duty_new7_i I0[19] -pin half_duty_new7_i I0[18] load net half_duty_new6[7] -attr @rip O[7] -pin half_duty_new5_i I0[7] -pin half_duty_new5_i__0 I0[7] -pin half_duty_new6_i O[7] -pin half_duty_new6_i__0 I0[7] -pin half_duty_new7_i I0[7] load net half_duty_new4[31] -attr @rip O[31] -pin half_duty_new3_i I1[31] -pin half_duty_new4_i__0 O[31] load net half_duty_new6[13] -attr @rip O[13] -pin half_duty_new5_i I0[13] -pin half_duty_new5_i__0 I0[13] -pin half_duty_new6_i O[13] -pin half_duty_new6_i__0 I0[13] -pin half_duty_new7_i I0[13] load net p_0_in[23] -attr @rip O[23] -pin half_duty_new2_i__0 I0[23] -pin half_duty_new2_i__1 I0[23] -pin half_duty_new3_i O[23] -pin half_duty_new3_i__0 I0[23] -pin half_duty_new4_i__1 I0[23] load net half_duty_new2[14] -attr @rip O[14] -pin half_duty_new1_i I0[14] -pin half_duty_new2_i__0 O[14] load net half_duty_new4[29] -attr @rip O[29] -pin half_duty_new3_i I1[29] -pin half_duty_new4_i__0 O[29] load net count_reg[0]__0[1] -attr @rip 1 -pin count[0]0_i I0[1] -pin count[0]_i S[1] -pin count_reg[0][8:0] Q[1] -pin half_duty[0]_i A[1] -pin pwm_out0_i I0[1] -pin pwm_out1_i__0 I0[1] load net half_duty_new2[4] -attr @rip O[4] -pin half_duty_new1_i I0[4] -pin half_duty_new2_i__0 O[4] load net half_duty_new3[25] -attr @rip O[25] -pin half_duty_new2_i__0 I1[25] -pin half_duty_new3_i__0 O[25] load net half_duty_new[1] -pin half_duty_new_reg[7:0] Q[1] -pin half_duty_reg[0][7:0] D[1] load net half_duty_new3[27] -attr @rip O[27] -pin half_duty_new2_i__0 I1[27] -pin half_duty_new3_i__0 O[27] load net ena -port ena -pin half_duty_new0_i__0 I0 netloc ena 1 0 11 NJ 270 NJ 270 NJ 270 NJ 270 NJ 270 NJ 270 NJ 270 NJ 270 NJ 270 NJ 270 3040J load net pwm_out1_i_n_0 -attr @rip O[9] -pin pwm_out0_i I1[31] -pin pwm_out0_i I1[30] -pin pwm_out0_i I1[29] -pin pwm_out0_i I1[28] -pin pwm_out0_i I1[27] -pin pwm_out0_i I1[26] -pin pwm_out0_i I1[25] -pin pwm_out0_i I1[24] -pin pwm_out0_i I1[23] -pin pwm_out0_i I1[22] -pin pwm_out0_i I1[21] -pin pwm_out0_i I1[20] -pin pwm_out0_i I1[19] -pin pwm_out0_i I1[18] -pin pwm_out0_i I1[17] -pin pwm_out0_i I1[16] -pin pwm_out0_i I1[15] -pin pwm_out0_i I1[14] -pin pwm_out0_i I1[13] -pin pwm_out0_i I1[12] -pin pwm_out0_i I1[11] -pin pwm_out0_i I1[10] -pin pwm_out0_i I1[9] -pin pwm_out1_i O[9] load net half_duty_new4[23] -attr @rip O[23] -pin half_duty_new3_i I1[23] -pin half_duty_new4_i__0 O[23] load net count[0][5] -attr @rip O[5] -pin count[0]_i O[5] -pin count_reg[0][8:0] D[5] load net pwm_out1_i_n_1 -attr @rip O[8] -pin pwm_out0_i I1[8] -pin pwm_out1_i O[8] load net pwm_out1_i_n_2 -attr @rip O[7] -pin pwm_out0_i I1[7] -pin pwm_out1_i O[7] load net half_duty_new5[8] -attr @rip O[8] -pin half_duty_new4_i I0[8] -pin half_duty_new5_i O[8] load net half_duty_new7 -pin half_duty_new5_i S -pin half_duty_new7_i O netloc half_duty_new7 1 2 1 NJ load net pwm_out1_i_n_3 -attr @rip O[6] -pin pwm_out0_i I1[6] -pin pwm_out1_i O[6] load net half_duty_new3[13] -attr @rip O[13] -pin half_duty_new2_i__0 I1[13] -pin half_duty_new3_i__0 O[13] load net count[0][2] -attr @rip O[2] -pin count[0]_i O[2] -pin count_reg[0][8:0] D[2] load net half_duty_new2[0] -attr @rip O[0] -pin half_duty_new1_i I0[0] -pin half_duty_new2_i__0 O[0] load net half_duty_new2[19] -attr @rip O[19] -pin half_duty_new1_i I0[19] -pin half_duty_new2_i__0 O[19] load net pwm_out1_i_n_4 -attr @rip O[5] -pin pwm_out0_i I1[5] -pin pwm_out1_i O[5] load net half_duty_new5[26] -attr @rip O[26] -pin half_duty_new4_i I0[26] -pin half_duty_new5_i O[26] load net -ground -pin count[0]_i I0[8] -pin count[0]_i I0[7] -pin count[0]_i I0[6] -pin count[0]_i I0[5] -pin count[0]_i I0[4] -pin count[0]_i I0[3] -pin count[0]_i I0[2] -pin count[0]_i I0[1] -pin count[0]_i I0[0] -pin half_duty_new0_i__0 I1 -pin half_duty_new2_i I1 -pin half_duty_new2_i__1 I1[31] -pin half_duty_new2_i__1 I1[30] -pin half_duty_new2_i__1 I1[29] -pin half_duty_new2_i__1 I1[28] -pin half_duty_new2_i__1 I1[27] -pin half_duty_new2_i__1 I1[26] -pin half_duty_new2_i__1 I1[25] -pin half_duty_new2_i__1 I1[24] -pin half_duty_new2_i__1 I1[23] -pin half_duty_new2_i__1 I1[22] -pin half_duty_new2_i__1 I1[21] -pin half_duty_new2_i__1 I1[20] -pin half_duty_new2_i__1 I1[19] -pin half_duty_new2_i__1 I1[18] -pin half_duty_new2_i__1 I1[17] -pin half_duty_new2_i__1 I1[16] -pin half_duty_new2_i__1 I1[15] -pin half_duty_new2_i__1 I1[14] -pin half_duty_new2_i__1 I1[13] -pin half_duty_new2_i__1 I1[12] -pin half_duty_new2_i__1 I1[11] -pin half_duty_new2_i__1 I1[10] -pin half_duty_new2_i__1 I1[9] -pin half_duty_new2_i__1 I1[8] -pin half_duty_new2_i__1 I1[7] -pin half_duty_new2_i__1 I1[6] -pin half_duty_new2_i__1 I1[5] -pin half_duty_new2_i__1 I1[4] -pin half_duty_new2_i__1 I1[3] -pin half_duty_new2_i__1 I1[2] -pin half_duty_new2_i__1 I1[1] -pin half_duty_new2_i__1 I1[0] -pin half_duty_new4_i I1[2] -pin half_duty_new4_i I1[1] -pin half_duty_new4_i I1[0] -pin half_duty_new4_i__1 I1[31] -pin half_duty_new4_i__1 I1[30] -pin half_duty_new4_i__1 I1[29] -pin half_duty_new4_i__1 I1[28] -pin half_duty_new4_i__1 I1[27] -pin half_duty_new4_i__1 I1[26] -pin half_duty_new4_i__1 I1[25] -pin half_duty_new4_i__1 I1[24] -pin half_duty_new4_i__1 I1[23] -pin half_duty_new4_i__1 I1[22] -pin half_duty_new4_i__1 I1[21] -pin half_duty_new4_i__1 I1[20] -pin half_duty_new4_i__1 I1[19] -pin half_duty_new4_i__1 I1[18] -pin half_duty_new4_i__1 I1[17] -pin half_duty_new4_i__1 I1[16] -pin half_duty_new4_i__1 I1[15] -pin half_duty_new4_i__1 I1[14] -pin half_duty_new4_i__1 I1[13] -pin half_duty_new4_i__1 I1[12] -pin half_duty_new4_i__1 I1[11] -pin half_duty_new4_i__1 I1[10] -pin half_duty_new4_i__1 I1[9] -pin half_duty_new4_i__1 I1[8] -pin half_duty_new4_i__1 I1[7] -pin half_duty_new4_i__1 I1[6] -pin half_duty_new4_i__1 I1[5] -pin half_duty_new4_i__1 I1[4] -pin half_duty_new4_i__1 I1[3] -pin half_duty_new4_i__1 I1[2] -pin half_duty_new4_i__1 I1[1] -pin half_duty_new4_i__1 I1[0] -pin half_duty_new5_i__0 I1[31] -pin half_duty_new5_i__0 I1[30] -pin half_duty_new5_i__0 I1[29] -pin half_duty_new5_i__0 I1[28] -pin half_duty_new5_i__0 I1[27] -pin half_duty_new5_i__0 I1[26] -pin half_duty_new5_i__0 I1[25] -pin half_duty_new5_i__0 I1[24] -pin half_duty_new5_i__0 I1[23] -pin half_duty_new5_i__0 I1[22] -pin half_duty_new5_i__0 I1[21] -pin half_duty_new5_i__0 I1[20] -pin half_duty_new5_i__0 I1[19] -pin half_duty_new5_i__0 I1[18] -pin half_duty_new5_i__0 I1[17] -pin half_duty_new5_i__0 I1[16] -pin half_duty_new5_i__0 I1[15] -pin half_duty_new5_i__0 I1[14] -pin half_duty_new5_i__0 I1[13] -pin half_duty_new5_i__0 I1[12] -pin half_duty_new5_i__0 I1[11] -pin half_duty_new5_i__0 I1[10] -pin half_duty_new5_i__0 I1[9] -pin half_duty_new5_i__0 I1[8] -pin half_duty_new5_i__0 I1[7] -pin half_duty_new5_i__0 I1[6] -pin half_duty_new5_i__0 I1[5] -pin half_duty_new5_i__0 I1[4] -pin half_duty_new5_i__0 I1[3] -pin half_duty_new5_i__0 I1[2] -pin half_duty_new5_i__0 I1[1] -pin half_duty_new5_i__0 I1[0] -pin half_duty_new6_i I0[8] -pin half_duty_new6_i I1[9] -pin half_duty_new6_i I1[3] -pin half_duty_new6_i I1[1] -pin half_duty_new6_i I1[0] -pin half_duty_new7_i I1[31] -pin half_duty_new7_i I1[30] -pin half_duty_new7_i I1[29] -pin half_duty_new7_i I1[28] -pin half_duty_new7_i I1[27] -pin half_duty_new7_i I1[26] -pin half_duty_new7_i I1[25] -pin half_duty_new7_i I1[24] -pin half_duty_new7_i I1[23] -pin half_duty_new7_i I1[22] -pin half_duty_new7_i I1[21] -pin half_duty_new7_i I1[20] -pin half_duty_new7_i I1[19] -pin half_duty_new7_i I1[18] -pin half_duty_new7_i I1[17] -pin half_duty_new7_i I1[16] -pin half_duty_new7_i I1[15] -pin half_duty_new7_i I1[14] -pin half_duty_new7_i I1[13] -pin half_duty_new7_i I1[12] -pin half_duty_new7_i I1[11] -pin half_duty_new7_i I1[10] -pin half_duty_new7_i I1[9] -pin half_duty_new7_i I1[8] -pin half_duty_new7_i I1[7] -pin half_duty_new7_i I1[6] -pin half_duty_new7_i I1[5] -pin half_duty_new7_i I1[4] -pin half_duty_new7_i I1[3] -pin half_duty_new7_i I1[2] -pin half_duty_new7_i I1[1] -pin half_duty_new7_i I1[0] -pin half_duty_reg[0]0_i I1 -pin pwm_out0_i I0[31] -pin pwm_out0_i I0[30] -pin pwm_out0_i I0[29] -pin pwm_out0_i I0[28] -pin pwm_out0_i I0[27] -pin pwm_out0_i I0[26] -pin pwm_out0_i I0[25] -pin pwm_out0_i I0[24] -pin pwm_out0_i I0[23] -pin pwm_out0_i I0[22] -pin pwm_out0_i I0[21] -pin pwm_out0_i I0[20] -pin pwm_out0_i I0[19] -pin pwm_out0_i I0[18] -pin pwm_out0_i I0[17] -pin pwm_out0_i I0[16] -pin pwm_out0_i I0[15] -pin pwm_out0_i I0[14] -pin pwm_out0_i I0[13] -pin pwm_out0_i I0[12] -pin pwm_out0_i I0[11] -pin pwm_out0_i I0[10] -pin pwm_out0_i I0[9] -pin pwm_out1_i I0[31] -pin pwm_out1_i I0[30] -pin pwm_out1_i I0[29] -pin pwm_out1_i I0[28] -pin pwm_out1_i I0[27] -pin pwm_out1_i I0[26] -pin pwm_out1_i I0[25] -pin pwm_out1_i I0[24] -pin pwm_out1_i I0[23] -pin pwm_out1_i I0[22] -pin pwm_out1_i I0[21] -pin pwm_out1_i I0[20] -pin pwm_out1_i I0[19] -pin pwm_out1_i I0[18] -pin pwm_out1_i I0[17] -pin pwm_out1_i I0[16] -pin pwm_out1_i I0[15] -pin pwm_out1_i I0[14] -pin pwm_out1_i I0[13] -pin pwm_out1_i I0[12] -pin pwm_out1_i I0[11] -pin pwm_out1_i I0[10] -pin pwm_out1_i I0[9] -pin pwm_out1_i I0[3] -pin pwm_out1_i I0[1] -pin pwm_out1_i I0[0] -pin pwm_out1_i__0 I1[8] -pin pwm_out_i I0 load net pwm_out1_i_n_5 -attr @rip O[4] -pin pwm_out0_i I1[4] -pin pwm_out1_i O[4] load net half_duty_new5[2] -attr @rip O[2] -pin half_duty_new4_i I0[2] -pin half_duty_new5_i O[2] load net pwm_out1_i_n_6 -attr @rip O[3] -pin pwm_out0_i I1[3] -pin pwm_out1_i O[3] load net half_duty_new4[19] -attr @rip O[19] -pin half_duty_new3_i I1[19] -pin half_duty_new4_i__0 O[19] load net pwm_out1_i_n_7 -attr @rip O[2] -pin pwm_out0_i I1[2] -pin pwm_out1_i O[2] load net half_duty_new1[5] -attr @rip O[5] -pin half_duty_new0_i I1[5] -pin half_duty_new1_i__0 O[5] load net pwm_out1_i_n_8 -attr @rip O[1] -pin pwm_out0_i I1[1] -pin pwm_out1_i O[1] load net pwm_out1_i_n_9 -attr @rip O[0] -pin pwm_out0_i I1[0] -pin pwm_out1_i O[0] load net half_duty_new4[30] -attr @rip O[30] -pin half_duty_new3_i I1[30] -pin half_duty_new4_i__0 O[30] load net half_duty_new6[12] -attr @rip O[12] -pin half_duty_new5_i I0[12] -pin half_duty_new5_i__0 I0[12] -pin half_duty_new6_i O[12] -pin half_duty_new6_i__0 I0[12] -pin half_duty_new7_i I0[12] load net p_0_in[22] -attr @rip O[22] -pin half_duty_new2_i__0 I0[22] -pin half_duty_new2_i__1 I0[22] -pin half_duty_new3_i O[22] -pin half_duty_new3_i__0 I0[22] -pin half_duty_new4_i__1 I0[22] load net half_duty_new5[22] -attr @rip O[22] -pin half_duty_new4_i I0[22] -pin half_duty_new5_i O[22] load net half_duty_new4[28] -attr @rip O[28] -pin half_duty_new3_i I1[28] -pin half_duty_new4_i__0 O[28] load net half_duty_new2[13] -attr @rip O[13] -pin half_duty_new1_i I0[13] -pin half_duty_new2_i__0 O[13] load net half_duty_new6[8] -attr @rip O[8] -pin half_duty_new5_i I0[8] -pin half_duty_new5_i__0 I0[8] -pin half_duty_new6_i O[8] -pin half_duty_new6_i__0 I0[8] -pin half_duty_new7_i I0[8] load net half_duty_new3[24] -attr @rip O[24] -pin half_duty_new2_i__0 I1[24] -pin half_duty_new3_i__0 O[24] load net half_duty_new2[3] -attr @rip O[3] -pin half_duty_new1_i I0[3] -pin half_duty_new2_i__0 O[3] load net half_duty_new[0] -pin half_duty_new_reg[7:0] Q[0] -pin half_duty_reg[0][7:0] D[0] load net half_duty_new[5] -pin half_duty_new_reg[7:0] Q[5] -pin half_duty_reg[0][7:0] D[5] load net half_duty_new3[28] -attr @rip O[28] -pin half_duty_new2_i__0 I1[28] -pin half_duty_new3_i__0 O[28] load net clk -port clk -pin count_reg[0][8:0] C -pin half_duty_new_reg[7:0] C -pin half_duty_reg[0][7:0] C -pin pwm_n_out_reg[0] C -pin pwm_out_reg[0] C netloc clk 1 0 17 NJ 190 NJ 190 NJ 190 NJ 190 NJ 190 NJ 190 NJ 190 NJ 190 NJ 190 2730 290 3060J 400 3390 410 3650 360 NJ 360 NJ 360 4490J 410 4780 load net count[0][4] -attr @rip O[4] -pin count[0]_i O[4] -pin count_reg[0][8:0] D[4] load net half_duty_new4[24] -attr @rip O[24] -pin half_duty_new3_i I1[24] -pin half_duty_new4_i__0 O[24] load net p_0_in[10] -attr @rip O[10] -pin half_duty_new2_i__0 I0[10] -pin half_duty_new2_i__1 I0[10] -pin half_duty_new3_i O[10] -pin half_duty_new3_i__0 I0[10] -pin half_duty_new4_i__1 I0[10] load net half_duty_new5[10] -attr @rip O[10] -pin half_duty_new4_i I0[10] -pin half_duty_new5_i O[10] load net half_duty_new1[0] -attr @rip O[0] -pin half_duty_new0_i I1[0] -pin half_duty_new1_i__0 O[0] load net half_duty_new1_i_n_0 -attr @rip O[7] -pin half_duty_new0_i I0[7] -pin half_duty_new1_i O[7] -pin half_duty_new1_i__0 I0[7] load net count_reg[0]__0[8] -attr @rip 8 -pin count[0]0_i I0[8] -pin count[0]_i S[8] -pin count_reg[0][8:0] Q[8] -pin half_duty[0]_i A[8] -pin pwm_out0_i I0[8] -pin pwm_out1_i__0 I0[8] load net half_duty_new1_i_n_1 -attr @rip O[6] -pin half_duty_new0_i I0[6] -pin half_duty_new1_i O[6] -pin half_duty_new1_i__0 I0[6] load net half_duty_new5[1] -attr @rip O[1] -pin half_duty_new4_i I0[1] -pin half_duty_new5_i O[1] load net count[0][3] -attr @rip O[3] -pin count[0]_i O[3] -pin count_reg[0][8:0] D[3] load net half_duty_new3[14] -attr @rip O[14] -pin half_duty_new2_i__0 I1[14] -pin half_duty_new3_i__0 O[14] load net half_duty_new1_i_n_2 -attr @rip O[5] -pin half_duty_new0_i I0[5] -pin half_duty_new1_i O[5] -pin half_duty_new1_i__0 I0[5] load net -power -pin count[0]0_i I1 -pin half_duty_new1_i I1 -pin half_duty_new1_i I2 -pin half_duty_new4_i I2 -pin half_duty_new4_i I1[3] -pin half_duty_new6_i I1[8] -pin half_duty_new6_i I1[7] -pin half_duty_new6_i I1[6] -pin half_duty_new6_i I1[5] -pin half_duty_new6_i I1[4] -pin half_duty_new6_i I1[2] -pin pwm_n_out_i I0 -pin pwm_out1_i I0[8] -pin pwm_out1_i I0[7] -pin pwm_out1_i I0[6] -pin pwm_out1_i I0[5] -pin pwm_out1_i I0[4] -pin pwm_out1_i I0[2] -pin pwm_out_i__0 I0 load net half_duty_new1_i_n_3 -attr @rip O[4] -pin half_duty_new0_i I0[4] -pin half_duty_new1_i O[4] -pin half_duty_new1_i__0 I0[4] load net half_duty_new4[10] -attr @rip O[10] -pin half_duty_new3_i I1[10] -pin half_duty_new4_i__0 O[10] load net half_duty_new1_i_n_4 -attr @rip O[3] -pin half_duty_new0_i I0[3] -pin half_duty_new1_i O[3] -pin half_duty_new1_i__0 I0[3] load net half_duty_new1_i_n_5 -attr @rip O[2] -pin half_duty_new0_i I0[2] -pin half_duty_new1_i O[2] -pin half_duty_new1_i__0 I0[2] load net half_duty_new6[11] -attr @rip O[11] -pin half_duty_new5_i I0[11] -pin half_duty_new5_i__0 I0[11] -pin half_duty_new6_i O[11] -pin half_duty_new6_i__0 I0[11] -pin half_duty_new7_i I0[11] load net p_0_in[4] -attr @rip O[4] -pin half_duty_new2_i__0 I0[4] -pin half_duty_new2_i__1 I0[4] -pin half_duty_new3_i O[4] -pin half_duty_new3_i__0 I0[4] -pin half_duty_new4_i__1 I0[4] load net half_duty_new1_i_n_6 -attr @rip O[1] -pin half_duty_new0_i I0[1] -pin half_duty_new1_i O[1] -pin half_duty_new1_i__0 I0[1] load net half_duty_new2[12] -attr @rip O[12] -pin half_duty_new1_i I0[12] -pin half_duty_new2_i__0 O[12] load net half_duty_new5[21] -attr @rip O[21] -pin half_duty_new4_i I0[21] -pin half_duty_new5_i O[21] load net half_duty_new1_i_n_7 -attr @rip O[0] -pin half_duty_new0_i I0[0] -pin half_duty_new1_i O[0] -pin half_duty_new1_i__0 I0[0] load net half_duty_new2[2] -attr @rip O[2] -pin half_duty_new1_i I0[2] -pin half_duty_new2_i__0 O[2] load net half_duty_new3[23] -attr @rip O[23] -pin half_duty_new2_i__0 I1[23] -pin half_duty_new3_i__0 O[23] load net half_duty_new6[5] -attr @rip O[5] -pin half_duty_new5_i I0[5] -pin half_duty_new5_i__0 I0[5] -pin half_duty_new6_i O[5] -pin half_duty_new6_i__0 I0[5] -pin half_duty_new7_i I0[5] load net half_duty_new[4] -pin half_duty_new_reg[7:0] Q[4] -pin half_duty_reg[0][7:0] D[4] load net duty[7] -attr @rip duty[7] -port duty[7] -pin half_duty_new6_i I0[7] load net half_duty_new6[9] -attr @rip O[9] -pin half_duty_new5_i I0[9] -pin half_duty_new5_i__0 I0[9] -pin half_duty_new6_i O[9] -pin half_duty_new6_i__0 I0[9] -pin half_duty_new7_i I0[9] load net half_duty_new2[30] -attr @rip O[30] -pin half_duty_new1_i I0[30] -pin half_duty_new2_i__0 O[30] load net p_0_in[25] -attr @rip O[25] -pin half_duty_new2_i__0 I0[25] -pin half_duty_new2_i__1 I0[25] -pin half_duty_new3_i O[25] -pin half_duty_new3_i__0 I0[25] -pin half_duty_new4_i__1 I0[25] load net half_duty_new[3] -pin half_duty_new_reg[7:0] Q[3] -pin half_duty_reg[0][7:0] D[3] load net half_duty_new3[29] -attr @rip O[29] -pin half_duty_new2_i__0 I1[29] -pin half_duty_new3_i__0 O[29] load net half_duty_new2_i__1_n_0 -pin half_duty_new0_i S -pin half_duty_new2_i__1 O netloc half_duty_new2_i__1_n_0 1 10 1 3100 load net half_duty_new5[19] -attr @rip O[19] -pin half_duty_new4_i I0[19] -pin half_duty_new5_i O[19] load net count_reg[0]__0[7] -attr @rip 7 -pin count[0]0_i I0[7] -pin count[0]_i S[7] -pin count_reg[0][8:0] Q[7] -pin half_duty[0]_i A[7] -pin pwm_out0_i I0[7] -pin pwm_out1_i__0 I0[7] load net count[0][7] -attr @rip O[7] -pin count[0]_i O[7] -pin count_reg[0][8:0] D[7] load net half_duty_new4[25] -attr @rip O[25] -pin half_duty_new3_i I1[25] -pin half_duty_new4_i__0 O[25] load net p_0_in[11] -attr @rip O[11] -pin half_duty_new2_i__0 I0[11] -pin half_duty_new2_i__1 I0[11] -pin half_duty_new3_i O[11] -pin half_duty_new3_i__0 I0[11] -pin half_duty_new4_i__1 I0[11] load net half_duty_new5[11] -attr @rip O[11] -pin half_duty_new4_i I0[11] -pin half_duty_new5_i O[11] load net half_duty_new4[17] -attr @rip O[17] -pin half_duty_new3_i I1[17] -pin half_duty_new4_i__0 O[17] load net half_duty_new3[15] -attr @rip O[15] -pin half_duty_new2_i__0 I1[15] -pin half_duty_new3_i__0 O[15] load net half_duty_new2[11] -attr @rip O[11] -pin half_duty_new1_i I0[11] -pin half_duty_new2_i__0 O[11] load net half_duty_new4[7] -attr @rip O[7] -pin half_duty_new3_i I1[7] -pin half_duty_new4_i__0 O[7] load net half_duty_new3[22] -attr @rip O[22] -pin half_duty_new2_i__0 I1[22] -pin half_duty_new3_i__0 O[22] load net half_duty_new6[4] -attr @rip O[4] -pin half_duty_new5_i I0[4] -pin half_duty_new5_i__0 I0[4] -pin half_duty_new6_i O[4] -pin half_duty_new6_i__0 I0[4] -pin half_duty_new7_i I0[4] load net p_0_in[5] -attr @rip O[5] -pin half_duty_new2_i__0 I0[5] -pin half_duty_new2_i__1 I0[5] -pin half_duty_new3_i O[5] -pin half_duty_new3_i__0 I0[5] -pin half_duty_new4_i__1 I0[5] load net count[0]0[8] -attr @rip O[8] -pin count[0]0_i O[8] -pin count[0]_i I1[8] load net half_duty_new6_i__0_n_0 -attr @rip O[30] -pin half_duty_new5_i I1[30] -pin half_duty_new6_i__0 O[30] load net half_duty_reg[0]0 -pin half_duty_reg[0]0_i O -pin half_duty_reg[0][7:0] CE netloc half_duty_reg[0]0 1 12 1 3670 load net half_duty_new6_i__0_n_1 -attr @rip O[29] -pin half_duty_new5_i I1[29] -pin half_duty_new6_i__0 O[29] load net p_0_in[24] -attr @rip O[24] -pin half_duty_new2_i__0 I0[24] -pin half_duty_new2_i__1 I0[24] -pin half_duty_new3_i O[24] -pin half_duty_new3_i__0 I0[24] -pin half_duty_new4_i__1 I0[24] load net half_duty_new2[26] -attr @rip O[26] -pin half_duty_new1_i I0[26] -pin half_duty_new2_i__0 O[26] load net half_duty_new5[24] -attr @rip O[24] -pin half_duty_new4_i I0[24] -pin half_duty_new5_i O[24] load net half_duty_new6_i__0_n_2 -attr @rip O[28] -pin half_duty_new5_i I1[28] -pin half_duty_new6_i__0 O[28] load net half_duty_new4_i__1_n_0 -pin half_duty_new2_i__0 S -pin half_duty_new4_i__1 O netloc half_duty_new4_i__1_n_0 1 7 1 2100 load net half_duty_new6_i__0_n_3 -attr @rip O[27] -pin half_duty_new5_i I1[27] -pin half_duty_new6_i__0 O[27] load net half_duty_new[2] -pin half_duty_new_reg[7:0] Q[2] -pin half_duty_reg[0][7:0] D[2] load net half_duty_new[7] -pin half_duty_new_reg[7:0] Q[7] -pin half_duty_reg[0][7:0] D[7] load net half_duty_new4[8] -attr @rip O[8] -pin half_duty_new3_i I1[8] -pin half_duty_new4_i__0 O[8] load net half_duty_new6_i__0_n_4 -attr @rip O[26] -pin half_duty_new5_i I1[26] -pin half_duty_new6_i__0 O[26] load net half_duty_new6_i__0_n_5 -attr @rip O[25] -pin half_duty_new5_i I1[25] -pin half_duty_new6_i__0 O[25] load net half_duty_new5[18] -attr @rip O[18] -pin half_duty_new4_i I0[18] -pin half_duty_new5_i O[18] load net half_duty_new6_i__0_n_6 -attr @rip O[24] -pin half_duty_new5_i I1[24] -pin half_duty_new6_i__0 O[24] load net count_reg[0]__0[6] -attr @rip 6 -pin count[0]0_i I0[6] -pin count[0]_i S[6] -pin count_reg[0][8:0] Q[6] -pin half_duty[0]_i A[6] -pin pwm_out0_i I0[6] -pin pwm_out1_i__0 I0[6] load net count[0][6] -attr @rip O[6] -pin count[0]_i O[6] -pin count_reg[0][8:0] D[6] load net half_duty_new2[9] -attr @rip O[9] -pin half_duty_new1_i I0[9] -pin half_duty_new2_i__0 O[9] load net half_duty_new6_i__0_n_7 -attr @rip O[23] -pin half_duty_new5_i I1[23] -pin half_duty_new6_i__0 O[23] load net half_duty_new3[6] -attr @rip O[6] -pin half_duty_new2_i__0 I1[6] -pin half_duty_new3_i__0 O[6] load net half_duty_new6_i__0_n_8 -attr @rip O[22] -pin half_duty_new5_i I1[22] -pin half_duty_new6_i__0 O[22] load net half_duty_new6_i__0_n_9 -attr @rip O[21] -pin half_duty_new5_i I1[21] -pin half_duty_new6_i__0 O[21] load net p_0_in[12] -attr @rip O[12] -pin half_duty_new2_i__0 I0[12] -pin half_duty_new2_i__1 I0[12] -pin half_duty_new3_i O[12] -pin half_duty_new3_i__0 I0[12] -pin half_duty_new4_i__1 I0[12] load net half_duty_new1[2] -attr @rip O[2] -pin half_duty_new0_i I1[2] -pin half_duty_new1_i__0 O[2] load net half_duty_new4[18] -attr @rip O[18] -pin half_duty_new3_i I1[18] -pin half_duty_new4_i__0 O[18] load net half_duty_new3[16] -attr @rip O[16] -pin half_duty_new2_i__0 I1[16] -pin half_duty_new3_i__0 O[16] load net half_duty_new4[6] -attr @rip O[6] -pin half_duty_new3_i I1[6] -pin half_duty_new4_i__0 O[6] load net half_duty_new2[10] -attr @rip O[10] -pin half_duty_new1_i I0[10] -pin half_duty_new2_i__0 O[10] load net half_duty_new5[29] -attr @rip O[29] -pin half_duty_new4_i I0[29] -pin half_duty_new5_i O[29] load net half_duty_new4[12] -attr @rip O[12] -pin half_duty_new3_i I1[12] -pin half_duty_new4_i__0 O[12] load net half_duty_new3[21] -attr @rip O[21] -pin half_duty_new2_i__0 I1[21] -pin half_duty_new3_i__0 O[21] load net half_duty_new6[3] -attr @rip O[3] -pin half_duty_new5_i I0[3] -pin half_duty_new5_i__0 I0[3] -pin half_duty_new6_i O[3] -pin half_duty_new6_i__0 I0[3] -pin half_duty_new7_i I0[3] load net count[0]0[7] -attr @rip O[7] -pin count[0]0_i O[7] -pin count[0]_i I1[7] load net half_duty_new0[3] -attr @rip O[3] -pin half_duty_new0_i O[3] -pin half_duty_new_reg[7:0] D[3] load net duty[5] -attr @rip duty[5] -port duty[5] -pin half_duty_new6_i I0[5] load net count[0]0[2] -attr @rip O[2] -pin count[0]0_i O[2] -pin count[0]_i I1[2] load net p_0_in[6] -attr @rip O[6] -pin half_duty_new2_i__0 I0[6] -pin half_duty_new2_i__1 I0[6] -pin half_duty_new3_i O[6] -pin half_duty_new3_i__0 I0[6] -pin half_duty_new4_i__1 I0[6] load net half_duty_new5[23] -attr @rip O[23] -pin half_duty_new4_i I0[23] -pin half_duty_new5_i O[23] load net half_duty_new5[30] -attr @rip O[30] -pin half_duty_new4_i I0[30] -pin half_duty_new5_i O[30] load net half_duty_new[6] -pin half_duty_new_reg[7:0] Q[6] -pin half_duty_reg[0][7:0] D[6] load net half_duty_new2[27] -attr @rip O[27] -pin half_duty_new1_i I0[27] -pin half_duty_new2_i__0 O[27] load net p_0_in[27] -attr @rip O[27] -pin half_duty_new2_i__0 I0[27] -pin half_duty_new2_i__1 I0[27] -pin half_duty_new3_i O[27] -pin half_duty_new3_i__0 I0[27] -pin half_duty_new4_i__1 I0[27] load net half_duty_new4[9] -attr @rip O[9] -pin half_duty_new3_i I1[9] -pin half_duty_new4_i__0 O[9] load net half_duty_new5[17] -attr @rip O[17] -pin half_duty_new4_i I0[17] -pin half_duty_new5_i O[17] load net half_duty_new2[8] -attr @rip O[8] -pin half_duty_new1_i I0[8] -pin half_duty_new2_i__0 O[8] load net count_reg[0]__0[0] -attr @rip 0 -pin count[0]0_i I0[0] -pin count[0]_i S[0] -pin count_reg[0][8:0] Q[0] -pin half_duty[0]_i A[0] -pin pwm_out0_i I0[0] -pin pwm_out1_i__0 I0[0] load net count_reg[0]__0[5] -attr @rip 5 -pin count[0]0_i I0[5] -pin count[0]_i S[5] -pin count_reg[0][8:0] Q[5] -pin half_duty[0]_i A[5] -pin pwm_out0_i I0[5] -pin pwm_out1_i__0 I0[5] load net half_duty_new3[5] -attr @rip O[5] -pin half_duty_new2_i__0 I1[5] -pin half_duty_new3_i__0 O[5] load net half_duty_new1[1] -attr @rip O[1] -pin half_duty_new0_i I1[1] -pin half_duty_new1_i__0 O[1] load net p_0_in[13] -attr @rip O[13] -pin half_duty_new2_i__0 I0[13] -pin half_duty_new2_i__1 I0[13] -pin half_duty_new3_i O[13] -pin half_duty_new3_i__0 I0[13] -pin half_duty_new4_i__1 I0[13] load net half_duty_new4[5] -attr @rip O[5] -pin half_duty_new3_i I1[5] -pin half_duty_new4_i__0 O[5] load net half_duty_new3[17] -attr @rip O[17] -pin half_duty_new2_i__0 I1[17] -pin half_duty_new3_i__0 O[17] load net half_duty_new4[11] -attr @rip O[11] -pin half_duty_new3_i I1[11] -pin half_duty_new4_i__0 O[11] load net half_duty_new3[20] -attr @rip O[20] -pin half_duty_new2_i__0 I1[20] -pin half_duty_new3_i__0 O[20] load net half_duty_new6[2] -attr @rip O[2] -pin half_duty_new5_i I0[2] -pin half_duty_new5_i__0 I0[2] -pin half_duty_new6_i O[2] -pin half_duty_new6_i__0 I0[2] -pin half_duty_new7_i I0[2] load net count[0]0[6] -attr @rip O[6] -pin count[0]0_i O[6] -pin count[0]_i I1[6] load net half_duty_new0[2] -attr @rip O[2] -pin half_duty_new0_i O[2] -pin half_duty_new_reg[7:0] D[2] load net half_duty_new0[7] -attr @rip O[7] -pin half_duty_new0_i O[7] -pin half_duty_new_reg[7:0] D[7] load net duty[6] -attr @rip duty[6] -port duty[6] -pin half_duty_new6_i I0[6] load net count[0]0[3] -attr @rip O[3] -pin count[0]0_i O[3] -pin count[0]_i I1[3] load net half_duty_new2[24] -attr @rip O[24] -pin half_duty_new1_i I0[24] -pin half_duty_new2_i__0 O[24] load net half_duty_new2[29] -attr @rip O[29] -pin half_duty_new1_i I0[29] -pin half_duty_new2_i__0 O[29] load net p_0_in[7] -attr @rip O[7] -pin half_duty_new2_i__0 I0[7] -pin half_duty_new2_i__1 I0[7] -pin half_duty_new3_i O[7] -pin half_duty_new3_i__0 I0[7] -pin half_duty_new4_i__1 I0[7] load net p_0_in[26] -attr @rip O[26] -pin half_duty_new2_i__0 I0[26] -pin half_duty_new2_i__1 I0[26] -pin half_duty_new3_i O[26] -pin half_duty_new3_i__0 I0[26] -pin half_duty_new4_i__1 I0[26] load net pwm_out0 -pin pwm_n_out_i I1 -pin pwm_out0_i O -pin pwm_out_i I1 -pin pwm_out_i__0 I1 netloc pwm_out0 1 15 1 4510 load net half_duty_new5[16] -attr @rip O[16] -pin half_duty_new4_i I0[16] -pin half_duty_new5_i O[16] load net pwm_out1 -pin pwm_n_out_i S -pin pwm_n_out_reg[0] D -pin pwm_out1_i__0 O -pin pwm_out_i S -pin pwm_out_i__0 S netloc pwm_out1 1 15 2 4470 N 4800 load net half_duty_new2[7] -attr @rip O[7] -pin half_duty_new1_i I0[7] -pin half_duty_new2_i__0 O[7] load net half_duty_new6_i__0_n_10 -attr @rip O[20] -pin half_duty_new5_i I1[20] -pin half_duty_new6_i__0 O[20] load net half_duty_new6_i__0_n_11 -attr @rip O[19] -pin half_duty_new5_i I1[19] -pin half_duty_new6_i__0 O[19] load net half_duty_new3[8] -attr @rip O[8] -pin half_duty_new2_i__0 I1[8] -pin half_duty_new3_i__0 O[8] load net half_duty_new3_i_n_0 -attr @rip O[31] -pin half_duty_new2_i__1 I0[31] -pin half_duty_new3_i O[31] -pin half_duty_new4_i__1 I0[31] load net half_duty_new6_i__0_n_12 -attr @rip O[18] -pin half_duty_new5_i I1[18] -pin half_duty_new6_i__0 O[18] load net p_0_in[0] -attr @rip O[0] -pin half_duty_new2_i__0 I0[0] -pin half_duty_new2_i__1 I0[0] -pin half_duty_new3_i O[0] -pin half_duty_new3_i__0 I0[0] -pin half_duty_new4_i__1 I0[0] load net half_duty_new4[4] -attr @rip O[4] -pin half_duty_new3_i I1[4] -pin half_duty_new4_i__0 O[4] load net half_duty_new6_i__0_n_13 -attr @rip O[17] -pin half_duty_new5_i I1[17] -pin half_duty_new6_i__0 O[17] load net p_0_in[14] -attr @rip O[14] -pin half_duty_new2_i__0 I0[14] -pin half_duty_new2_i__1 I0[14] -pin half_duty_new3_i O[14] -pin half_duty_new3_i__0 I0[14] -pin half_duty_new4_i__1 I0[14] load net half_duty_new5[14] -attr @rip O[14] -pin half_duty_new4_i I0[14] -pin half_duty_new5_i O[14] load net half_duty_new6_i__0_n_14 -attr @rip O[16] -pin half_duty_new5_i I1[16] -pin half_duty_new6_i__0 O[16] load net half_duty_new0[1] -attr @rip O[1] -pin half_duty_new0_i O[1] -pin half_duty_new_reg[7:0] D[1] load net half_duty_new0[6] -attr @rip O[6] -pin half_duty_new0_i O[6] -pin half_duty_new_reg[7:0] D[6] load net duty[3] -attr @rip duty[3] -port duty[3] -pin half_duty_new6_i I0[3] load net count[0]0[0] -attr @rip O[0] -pin count[0]0_i O[0] -pin count[0]_i I1[0] load net count[0]0[5] -attr @rip O[5] -pin count[0]0_i O[5] -pin count[0]_i I1[5] load net half_duty_new6_i__0_n_15 -attr @rip O[15] -pin half_duty_new5_i I1[15] -pin half_duty_new6_i__0 O[15] load net half_duty_new0_i__0_n_0 -pin half_duty_new0_i__0 O -pin half_duty_new_reg[7:0] CE netloc half_duty_new0_i__0_n_0 1 11 1 3370 load net half_duty_new6_i__0_n_16 -attr @rip O[14] -pin half_duty_new5_i I1[14] -pin half_duty_new6_i__0 O[14] load net half_duty_new2[28] -attr @rip O[28] -pin half_duty_new1_i I0[28] -pin half_duty_new2_i__0 O[28] load net half_duty_new6_i__0_n_17 -attr @rip O[13] -pin half_duty_new5_i I1[13] -pin half_duty_new6_i__0 O[13] load net half_duty_reg[0]__0[7] -attr @rip 7 -pin half_duty_reg[0][7:0] Q[7] -pin pwm_out1_i I1[7] -pin pwm_out1_i__0 I1[7] load net half_duty_new4[14] -attr @rip O[14] -pin half_duty_new3_i I1[14] -pin half_duty_new4_i__0 O[14] load net half_duty_new6_i__0_n_18 -attr @rip O[12] -pin half_duty_new5_i I1[12] -pin half_duty_new6_i__0 O[12] load net half_duty_new2[25] -attr @rip O[25] -pin half_duty_new1_i I0[25] -pin half_duty_new2_i__0 O[25] load net half_duty_new6_i__0_n_19 -attr @rip O[11] -pin half_duty_new5_i I1[11] -pin half_duty_new6_i__0 O[11] load net half_duty_new5[4] -attr @rip O[4] -pin half_duty_new4_i I0[4] -pin half_duty_new5_i O[4] load net half_duty_new6[10] -attr @rip O[10] -pin half_duty_new5_i I0[10] -pin half_duty_new5_i__0 I0[10] -pin half_duty_new6_i O[10] -pin half_duty_new6_i__0 I0[10] -pin half_duty_new7_i I0[10] load net half_duty_new1[7] -attr @rip O[7] -pin half_duty_new0_i I1[7] -pin half_duty_new1_i__0 O[7] load net half_duty_new2[6] -attr @rip O[6] -pin half_duty_new1_i I0[6] -pin half_duty_new2_i__0 O[6] load net p_0_in[29] -attr @rip O[29] -pin half_duty_new2_i__0 I0[29] -pin half_duty_new2_i__1 I0[29] -pin half_duty_new3_i O[29] -pin half_duty_new3_i__0 I0[29] -pin half_duty_new4_i__1 I0[29] load net half_duty[0] -pin half_duty[0]_i O -pin half_duty_reg[0]0_i I0 netloc half_duty[0] 1 11 1 N load net half_duty_new3[7] -attr @rip O[7] -pin half_duty_new2_i__0 I1[7] -pin half_duty_new3_i__0 O[7] load net half_duty_new6_i__0_n_20 -attr @rip O[10] -pin half_duty_new5_i I1[10] -pin half_duty_new6_i__0 O[10] load net half_duty_new4[3] -attr @rip O[3] -pin half_duty_new3_i I1[3] -pin half_duty_new4_i__0 O[3] load net half_duty_new6_i__0_n_21 -attr @rip O[9] -pin half_duty_new5_i I1[9] -pin half_duty_new6_i__0 O[9] load net half_duty_new6_i__0_n_22 -attr @rip O[8] -pin half_duty_new5_i I1[8] -pin half_duty_new6_i__0 O[8] load net p_0_in[1] -attr @rip O[1] -pin half_duty_new2_i__0 I0[1] -pin half_duty_new2_i__1 I0[1] -pin half_duty_new3_i O[1] -pin half_duty_new3_i__0 I0[1] -pin half_duty_new4_i__1 I0[1] load net reset_n -pin half_duty_new2_i I0 -port reset_n netloc reset_n 1 0 9 NJ 610 NJ 610 NJ 610 NJ 610 NJ 610 NJ 610 NJ 610 NJ 610 NJ load net count[0]0[4] -attr @rip O[4] -pin count[0]0_i O[4] -pin count[0]_i I1[4] load net half_duty_new0[0] -attr @rip O[0] -pin half_duty_new0_i O[0] -pin half_duty_new_reg[7:0] D[0] load net half_duty_new0[5] -attr @rip O[5] -pin half_duty_new0_i O[5] -pin half_duty_new_reg[7:0] D[5] load net half_duty_new6_i__0_n_23 -attr @rip O[7] -pin half_duty_new5_i I1[7] -pin half_duty_new6_i__0 O[7] load net p_0_in[15] -attr @rip O[15] -pin half_duty_new2_i__0 I0[15] -pin half_duty_new2_i__1 I0[15] -pin half_duty_new3_i O[15] -pin half_duty_new3_i__0 I0[15] -pin half_duty_new4_i__1 I0[15] load net half_duty_new5[15] -attr @rip O[15] -pin half_duty_new4_i I0[15] -pin half_duty_new5_i O[15] load net half_duty_new6_i__0_n_24 -attr @rip O[6] -pin half_duty_new5_i I1[6] -pin half_duty_new6_i__0 O[6] load net half_duty_new2[22] -attr @rip O[22] -pin half_duty_new1_i I0[22] -pin half_duty_new2_i__0 O[22] load net half_duty_new3[19] -attr @rip O[19] -pin half_duty_new2_i__0 I1[19] -pin half_duty_new3_i__0 O[19] load net duty[4] -attr @rip duty[4] -port duty[4] -pin half_duty_new6_i I0[4] load net count[0]0[1] -attr @rip O[1] -pin count[0]0_i O[1] -pin count[0]_i I1[1] load net half_duty_new6_i__0_n_25 -attr @rip O[5] -pin half_duty_new5_i I1[5] -pin half_duty_new6_i__0 O[5] load net half_duty_reg[0]__0[6] -attr @rip 6 -pin half_duty_reg[0][7:0] Q[6] -pin pwm_out1_i I1[6] -pin pwm_out1_i__0 I1[6] load net half_duty_new4[13] -attr @rip O[13] -pin half_duty_new3_i I1[13] -pin half_duty_new4_i__0 O[13] load net half_duty_new6_i__0_n_26 -attr @rip O[4] -pin half_duty_new5_i I1[4] -pin half_duty_new6_i__0 O[4] load net half_duty_new6_i__0_n_27 -attr @rip O[3] -pin half_duty_new5_i I1[3] -pin half_duty_new6_i__0 O[3] load net half_duty_new5[3] -attr @rip O[3] -pin half_duty_new4_i I0[3] -pin half_duty_new5_i O[3] load net half_duty_new6_i__0_n_28 -attr @rip O[2] -pin half_duty_new5_i I1[2] -pin half_duty_new6_i__0 O[2] load net half_duty_new5_i__0_n_0 -pin half_duty_new3_i S -pin half_duty_new5_i__0 O netloc half_duty_new5_i__0_n_0 1 5 1 N load net half_duty_new6_i__0_n_29 -attr @rip O[1] -pin half_duty_new5_i I1[1] -pin half_duty_new6_i__0 O[1] load net half_duty_new3[2] -attr @rip O[2] -pin half_duty_new2_i__0 I1[2] -pin half_duty_new3_i__0 O[2] load net half_duty_new3[9] -attr @rip O[9] -pin half_duty_new2_i__0 I1[9] -pin half_duty_new3_i__0 O[9] load net p_0_in[28] -attr @rip O[28] -pin half_duty_new2_i__0 I0[28] -pin half_duty_new2_i__1 I0[28] -pin half_duty_new3_i O[28] -pin half_duty_new3_i__0 I0[28] -pin half_duty_new4_i__1 I0[28] load net pwm_out_i_n_0 -pin pwm_out_i O -pin pwm_out_reg[0] D netloc pwm_out_i_n_0 1 16 1 4760 load net half_duty_new2_i_n_0 -pin count_reg[0][8:0] CLR -pin half_duty_new0_i__0 S -pin half_duty_new2_i O -pin half_duty_reg[0]0_i S -pin pwm_n_out_reg[0] CLR -pin pwm_out_reg[0] CLR netloc half_duty_new2_i_n_0 1 9 8 2750 N 3060 N 3350 N NJ 140 NJ 140 NJ 140 4470J 120 4820 load net half_duty_new4[2] -attr @rip O[2] -pin half_duty_new3_i I1[2] -pin half_duty_new4_i__0 O[2] load net half_duty_new2[18] -attr @rip O[18] -pin half_duty_new1_i I0[18] -pin half_duty_new2_i__0 O[18] load net half_duty_new5[12] -attr @rip O[12] -pin half_duty_new4_i I0[12] -pin half_duty_new5_i O[12] load net duty[1] -attr @rip duty[1] -port duty[1] -pin half_duty_new6_i I0[1] load net half_duty_new0[4] -attr @rip O[4] -pin half_duty_new0_i O[4] -pin half_duty_new_reg[7:0] D[4] load net half_duty_new4_i_n_0 -attr @rip O[30] -pin half_duty_new3_i I0[30] -pin half_duty_new4_i O[30] -pin half_duty_new4_i__0 I0[30] load net p_0_in[2] -attr @rip O[2] -pin half_duty_new2_i__0 I0[2] -pin half_duty_new2_i__1 I0[2] -pin half_duty_new3_i O[2] -pin half_duty_new3_i__0 I0[2] -pin half_duty_new4_i__1 I0[2] load net half_duty_new4_i_n_1 -attr @rip O[29] -pin half_duty_new3_i I0[29] -pin half_duty_new4_i O[29] -pin half_duty_new4_i__0 I0[29] load net half_duty_new3[18] -attr @rip O[18] -pin half_duty_new2_i__0 I1[18] -pin half_duty_new3_i__0 O[18] load net half_duty_reg[0]__0[0] -attr @rip 0 -pin half_duty_reg[0][7:0] Q[0] -pin pwm_out1_i I1[0] -pin pwm_out1_i__0 I1[0] load net half_duty_reg[0]__0[5] -attr @rip 5 -pin half_duty_reg[0][7:0] Q[5] -pin pwm_out1_i I1[5] -pin pwm_out1_i__0 I1[5] load net p_0_in[16] -attr @rip O[16] -pin half_duty_new2_i__0 I0[16] -pin half_duty_new2_i__1 I0[16] -pin half_duty_new3_i O[16] -pin half_duty_new3_i__0 I0[16] -pin half_duty_new4_i__1 I0[16] load net half_duty_new4_i_n_2 -attr @rip O[28] -pin half_duty_new3_i I0[28] -pin half_duty_new4_i O[28] -pin half_duty_new4_i__0 I0[28] load net half_duty_new4_i_n_3 -attr @rip O[27] -pin half_duty_new3_i I0[27] -pin half_duty_new4_i O[27] -pin half_duty_new4_i__0 I0[27] load net half_duty_new2[23] -attr @rip O[23] -pin half_duty_new1_i I0[23] -pin half_duty_new2_i__0 O[23] load net half_duty_new4_i_n_4 -attr @rip O[26] -pin half_duty_new3_i I0[26] -pin half_duty_new4_i O[26] -pin half_duty_new4_i__0 I0[26] load net half_duty_new4_i_n_5 -attr @rip O[25] -pin half_duty_new3_i I0[25] -pin half_duty_new4_i O[25] -pin half_duty_new4_i__0 I0[25] load net half_duty_new6[15] -attr @rip O[15] -pin half_duty_new5_i I0[15] -pin half_duty_new5_i__0 I0[15] -pin half_duty_new6_i O[15] -pin half_duty_new6_i__0 I0[15] -pin half_duty_new7_i I0[15] load net half_duty_new4_i_n_6 -attr @rip O[24] -pin half_duty_new3_i I0[24] -pin half_duty_new4_i O[24] -pin half_duty_new4_i__0 I0[24] load net half_duty_new4[16] -attr @rip O[16] -pin half_duty_new3_i I1[16] -pin half_duty_new4_i__0 O[16] load net half_duty_new4_i_n_20 -attr @rip O[10] -pin half_duty_new3_i I0[10] -pin half_duty_new4_i O[10] -pin half_duty_new4_i__0 I0[10] load net half_duty_new3[1] -attr @rip O[1] -pin half_duty_new2_i__0 I1[1] -pin half_duty_new3_i__0 O[1] load net half_duty_new4_i_n_7 -attr @rip O[23] -pin half_duty_new3_i I0[23] -pin half_duty_new4_i O[23] -pin half_duty_new4_i__0 I0[23] load net half_duty_new4_i_n_21 -attr @rip O[9] -pin half_duty_new3_i I0[9] -pin half_duty_new4_i O[9] -pin half_duty_new4_i__0 I0[9] load net half_duty_new4_i_n_8 -attr @rip O[22] -pin half_duty_new3_i I0[22] -pin half_duty_new4_i O[22] -pin half_duty_new4_i__0 I0[22] load net half_duty_new5[6] -attr @rip O[6] -pin half_duty_new4_i I0[6] -pin half_duty_new5_i O[6] load net half_duty_new4_i_n_22 -attr @rip O[8] -pin half_duty_new3_i I0[8] -pin half_duty_new4_i O[8] -pin half_duty_new4_i__0 I0[8] load net half_duty_new4_i_n_9 -attr @rip O[21] -pin half_duty_new3_i I0[21] -pin half_duty_new4_i O[21] -pin half_duty_new4_i__0 I0[21] load net half_duty_new4_i_n_23 -attr @rip O[7] -pin half_duty_new3_i I0[7] -pin half_duty_new4_i O[7] -pin half_duty_new4_i__0 I0[7] load net half_duty_new3[0] -attr @rip O[0] -pin half_duty_new2_i__0 I1[0] -pin half_duty_new3_i__0 O[0] load net half_duty_new4_i_n_24 -attr @rip O[6] -pin half_duty_new3_i I0[6] -pin half_duty_new4_i O[6] -pin half_duty_new4_i__0 I0[6] load net half_duty_new4_i_n_25 -attr @rip O[5] -pin half_duty_new3_i I0[5] -pin half_duty_new4_i O[5] -pin half_duty_new4_i__0 I0[5] load net half_duty_new4[1] -attr @rip O[1] -pin half_duty_new3_i I1[1] -pin half_duty_new4_i__0 O[1] load net half_duty_new4[20] -attr @rip O[20] -pin half_duty_new3_i I1[20] -pin half_duty_new4_i__0 O[20] load net half_duty_new4_i_n_26 -attr @rip O[4] -pin half_duty_new3_i I0[4] -pin half_duty_new4_i O[4] -pin half_duty_new4_i__0 I0[4] load net half_duty_new2[17] -attr @rip O[17] -pin half_duty_new1_i I0[17] -pin half_duty_new2_i__0 O[17] load net count_reg[0]__0[4] -attr @rip 4 -pin count[0]0_i I0[4] -pin count[0]_i S[4] -pin count_reg[0][8:0] Q[4] -pin half_duty[0]_i A[4] -pin pwm_out0_i I0[4] -pin pwm_out1_i__0 I0[4] load net half_duty_new4_i_n_27 -attr @rip O[3] -pin half_duty_new3_i I0[3] -pin half_duty_new4_i O[3] -pin half_duty_new4_i__0 I0[3] load net half_duty_new5[13] -attr @rip O[13] -pin half_duty_new4_i I0[13] -pin half_duty_new5_i O[13] load net half_duty_new4_i_n_28 -attr @rip O[2] -pin half_duty_new3_i I0[2] -pin half_duty_new4_i O[2] -pin half_duty_new4_i__0 I0[2] load net half_duty_new3[10] -attr @rip O[10] -pin half_duty_new2_i__0 I1[10] -pin half_duty_new3_i__0 O[10] load net half_duty_new4_i_n_29 -attr @rip O[1] -pin half_duty_new3_i I0[1] -pin half_duty_new4_i O[1] -pin half_duty_new4_i__0 I0[1] load net duty[2] -attr @rip duty[2] -port duty[2] -pin half_duty_new6_i I0[2] load net half_duty_new2[20] -attr @rip O[20] -pin half_duty_new1_i I0[20] -pin half_duty_new2_i__0 O[20] load net half_duty_reg[0]__0[4] -attr @rip 4 -pin half_duty_reg[0][7:0] Q[4] -pin pwm_out1_i I1[4] -pin pwm_out1_i__0 I1[4] load net p_0_in[3] -attr @rip O[3] -pin half_duty_new2_i__0 I0[3] -pin half_duty_new2_i__1 I0[3] -pin half_duty_new3_i O[3] -pin half_duty_new3_i__0 I0[3] -pin half_duty_new4_i__1 I0[3] load net count[0][8] -attr @rip O[8] -pin count[0]_i O[8] -pin count_reg[0][8:0] D[8] load net half_duty_new5[9] -attr @rip O[9] -pin half_duty_new4_i I0[9] -pin half_duty_new5_i O[9] load net half_duty_reg[0]__0[1] -attr @rip 1 -pin half_duty_reg[0][7:0] Q[1] -pin pwm_out1_i I1[1] -pin pwm_out1_i__0 I1[1] load net p_0_in[17] -attr @rip O[17] -pin half_duty_new2_i__0 I0[17] -pin half_duty_new2_i__1 I0[17] -pin half_duty_new3_i O[17] -pin half_duty_new3_i__0 I0[17] -pin half_duty_new4_i__1 I0[17] load net half_duty_new5[27] -attr @rip O[27] -pin half_duty_new4_i I0[27] -pin half_duty_new5_i O[27] load net half_duty_new1[4] -attr @rip O[4] -pin half_duty_new0_i I1[4] -pin half_duty_new1_i__0 O[4] load net half_duty_new4[15] -attr @rip O[15] -pin half_duty_new3_i I1[15] -pin half_duty_new4_i__0 O[15] load net half_duty_new6[1] -attr @rip O[1] -pin half_duty_new5_i I0[1] -pin half_duty_new5_i__0 I0[1] -pin half_duty_new6_i O[1] -pin half_duty_new6_i__0 I0[1] -pin half_duty_new7_i I0[1] load net half_duty_new4_i_n_10 -attr @rip O[20] -pin half_duty_new3_i I0[20] -pin half_duty_new4_i O[20] -pin half_duty_new4_i__0 I0[20] load net half_duty_new6[16] -attr @rip O[16] -pin half_duty_new5_i I0[16] -pin half_duty_new5_i__0 I0[16] -pin half_duty_new6_i O[16] -pin half_duty_new6_i__0 I0[16] -pin half_duty_new7_i I0[16] load net half_duty_new4_i_n_11 -attr @rip O[19] -pin half_duty_new3_i I0[19] -pin half_duty_new4_i O[19] -pin half_duty_new4_i__0 I0[19] load net half_duty_new5[5] -attr @rip O[5] -pin half_duty_new4_i I0[5] -pin half_duty_new5_i O[5] load net p_0_in[21] -attr @rip O[21] -pin half_duty_new2_i__0 I0[21] -pin half_duty_new2_i__1 I0[21] -pin half_duty_new3_i O[21] -pin half_duty_new3_i__0 I0[21] -pin half_duty_new4_i__1 I0[21] load net half_duty_new4[27] -attr @rip O[27] -pin half_duty_new3_i I1[27] -pin half_duty_new4_i__0 O[27] load net half_duty_new4_i_n_12 -attr @rip O[18] -pin half_duty_new3_i I0[18] -pin half_duty_new4_i O[18] -pin half_duty_new4_i__0 I0[18] load net half_duty_new4_i_n_13 -attr @rip O[17] -pin half_duty_new3_i I0[17] -pin half_duty_new4_i O[17] -pin half_duty_new4_i__0 I0[17] load net half_duty_new4_i_n_14 -attr @rip O[16] -pin half_duty_new3_i I0[16] -pin half_duty_new4_i O[16] -pin half_duty_new4_i__0 I0[16] load net half_duty_new3[4] -attr @rip O[4] -pin half_duty_new2_i__0 I1[4] -pin half_duty_new3_i__0 O[4] load net half_duty_new4[0] -attr @rip O[0] -pin half_duty_new3_i I1[0] -pin half_duty_new4_i__0 O[0] load net half_duty_new4_i_n_15 -attr @rip O[15] -pin half_duty_new3_i I0[15] -pin half_duty_new4_i O[15] -pin half_duty_new4_i__0 I0[15] load net p_0_in[8] -attr @rip O[8] -pin half_duty_new2_i__0 I0[8] -pin half_duty_new2_i__1 I0[8] -pin half_duty_new3_i O[8] -pin half_duty_new3_i__0 I0[8] -pin half_duty_new4_i__1 I0[8] load net half_duty_new4_i_n_16 -attr @rip O[14] -pin half_duty_new3_i I0[14] -pin half_duty_new4_i O[14] -pin half_duty_new4_i__0 I0[14] load net half_duty_new2[16] -attr @rip O[16] -pin half_duty_new1_i I0[16] -pin half_duty_new2_i__0 O[16] load net half_duty_new4[21] -attr @rip O[21] -pin half_duty_new3_i I1[21] -pin half_duty_new4_i__0 O[21] load net count_reg[0]__0[3] -attr @rip 3 -pin count[0]0_i I0[3] -pin count[0]_i S[3] -pin count_reg[0][8:0] Q[3] -pin half_duty[0]_i A[3] -pin pwm_out0_i I0[3] -pin pwm_out1_i__0 I0[3] load net half_duty_new4_i_n_17 -attr @rip O[13] -pin half_duty_new3_i I0[13] -pin half_duty_new4_i O[13] -pin half_duty_new4_i__0 I0[13] load net half_duty_new4_i_n_18 -attr @rip O[12] -pin half_duty_new3_i I0[12] -pin half_duty_new4_i O[12] -pin half_duty_new4_i__0 I0[12] load net half_duty_new4_i_n_19 -attr @rip O[11] -pin half_duty_new3_i I0[11] -pin half_duty_new4_i O[11] -pin half_duty_new4_i__0 I0[11] load net half_duty_reg[0]__0[3] -attr @rip 3 -pin half_duty_reg[0][7:0] Q[3] -pin pwm_out1_i I1[3] -pin pwm_out1_i__0 I1[3] load net count[0][0] -attr @rip O[0] -pin count[0]_i O[0] -pin count_reg[0][8:0] D[0] load net half_duty_new3[11] -attr @rip O[11] -pin half_duty_new2_i__0 I1[11] -pin half_duty_new3_i__0 O[11] load net half_duty_new2[21] -attr @rip O[21] -pin half_duty_new1_i I0[21] -pin half_duty_new2_i__0 O[21] load net half_duty_new5[0] -attr @rip O[0] -pin half_duty_new4_i I0[0] -pin half_duty_new5_i O[0] load net p_0_in[18] -attr @rip O[18] -pin half_duty_new2_i__0 I0[18] -pin half_duty_new2_i__1 I0[18] -pin half_duty_new3_i O[18] -pin half_duty_new3_i__0 I0[18] -pin half_duty_new4_i__1 I0[18] load net half_duty_new1[3] -attr @rip O[3] -pin half_duty_new0_i I1[3] -pin half_duty_new1_i__0 O[3] load net half_duty_new6[0] -attr @rip O[0] -pin half_duty_new5_i I0[0] -pin half_duty_new5_i__0 I0[0] -pin half_duty_new6_i O[0] -pin half_duty_new6_i__0 I0[0] -pin half_duty_new7_i I0[0] load net half_duty_new5[28] -attr @rip O[28] -pin half_duty_new4_i I0[28] -pin half_duty_new5_i O[28] load net p_0_in[20] -attr @rip O[20] -pin half_duty_new2_i__0 I0[20] -pin half_duty_new2_i__1 I0[20] -pin half_duty_new3_i O[20] -pin half_duty_new3_i__0 I0[20] -pin half_duty_new4_i__1 I0[20] load net half_duty_new5[20] -attr @rip O[20] -pin half_duty_new4_i I0[20] -pin half_duty_new5_i O[20] load net half_duty_new4[26] -attr @rip O[26] -pin half_duty_new3_i I1[26] -pin half_duty_new4_i__0 O[26] load net half_duty_new6[17] -attr @rip O[17] -pin half_duty_new5_i I0[17] -pin half_duty_new5_i__0 I0[17] -pin half_duty_new6_i O[17] -pin half_duty_new6_i__0 I0[17] -pin half_duty_new7_i I0[17] load net half_duty_new6[6] -attr @rip O[6] -pin half_duty_new5_i I0[6] -pin half_duty_new5_i__0 I0[6] -pin half_duty_new6_i O[6] -pin half_duty_new6_i__0 I0[6] -pin half_duty_new7_i I0[6] load net half_duty_new3[3] -attr @rip O[3] -pin half_duty_new2_i__0 I1[3] -pin half_duty_new3_i__0 O[3] load net half_duty_new6[14] -attr @rip O[14] -pin half_duty_new5_i I0[14] -pin half_duty_new5_i__0 I0[14] -pin half_duty_new6_i O[14] -pin half_duty_new6_i__0 I0[14] -pin half_duty_new7_i I0[14] load netBundle @half_duty_new6 19 half_duty_new6[18] half_duty_new6[17] half_duty_new6[16] half_duty_new6[15] half_duty_new6[14] half_duty_new6[13] half_duty_new6[12] half_duty_new6[11] half_duty_new6[10] half_duty_new6[9] half_duty_new6[8] half_duty_new6[7] half_duty_new6[6] half_duty_new6[5] half_duty_new6[4] half_duty_new6[3] half_duty_new6[2] half_duty_new6[1] half_duty_new6[0] -autobundled netbloc @half_duty_new6 1 1 4 390 400 680 420 NJ 420 NJ load netBundle @half_duty_reg 8 half_duty_reg[0]__0[7] half_duty_reg[0]__0[6] half_duty_reg[0]__0[5] half_duty_reg[0]__0[4] half_duty_reg[0]__0[3] half_duty_reg[0]__0[2] half_duty_reg[0]__0[1] half_duty_reg[0]__0[0] -autobundled netbloc @half_duty_reg 1 13 2 3870 500 4200 load netBundle @half_duty_new6_i__0_n_0 31 half_duty_new6_i__0_n_0 half_duty_new6_i__0_n_1 half_duty_new6_i__0_n_2 half_duty_new6_i__0_n_3 half_duty_new6_i__0_n_4 half_duty_new6_i__0_n_5 half_duty_new6_i__0_n_6 half_duty_new6_i__0_n_7 half_duty_new6_i__0_n_8 half_duty_new6_i__0_n_9 half_duty_new6_i__0_n_10 half_duty_new6_i__0_n_11 half_duty_new6_i__0_n_12 half_duty_new6_i__0_n_13 half_duty_new6_i__0_n_14 half_duty_new6_i__0_n_15 half_duty_new6_i__0_n_16 half_duty_new6_i__0_n_17 half_duty_new6_i__0_n_18 half_duty_new6_i__0_n_19 half_duty_new6_i__0_n_20 half_duty_new6_i__0_n_21 half_duty_new6_i__0_n_22 half_duty_new6_i__0_n_23 half_duty_new6_i__0_n_24 half_duty_new6_i__0_n_25 half_duty_new6_i__0_n_26 half_duty_new6_i__0_n_27 half_duty_new6_i__0_n_28 half_duty_new6_i__0_n_29 half_duty_new6_i__0_n_30 -autobundled netbloc @half_duty_new6_i__0_n_0 1 2 1 660J load netBundle @p_0_in,half_duty_new3_i_n_0 32 half_duty_new3_i_n_0 p_0_in[30] p_0_in[29] p_0_in[28] p_0_in[27] p_0_in[26] p_0_in[25] p_0_in[24] p_0_in[23] p_0_in[22] p_0_in[21] p_0_in[20] p_0_in[19] p_0_in[18] p_0_in[17] p_0_in[16] p_0_in[15] p_0_in[14] p_0_in[13] p_0_in[12] p_0_in[11] p_0_in[10] p_0_in[9] p_0_in[8] p_0_in[7] p_0_in[6] p_0_in[5] p_0_in[4] p_0_in[3] p_0_in[2] p_0_in[1] p_0_in[0] -autobundled netbloc @p_0_in,half_duty_new3_i_n_0 1 6 4 1810 490 2100 440 NJ 440 NJ load netBundle @half_duty_new1_i_n_0 8 half_duty_new1_i_n_0 half_duty_new1_i_n_1 half_duty_new1_i_n_2 half_duty_new1_i_n_3 half_duty_new1_i_n_4 half_duty_new1_i_n_5 half_duty_new1_i_n_6 half_duty_new1_i_n_7 -autobundled netbloc @half_duty_new1_i_n_0 1 9 2 2770 310 N load netBundle @pwm_out1_i_n_0,pwm_out1_i_n_1 10 pwm_out1_i_n_0 pwm_out1_i_n_1 pwm_out1_i_n_2 pwm_out1_i_n_3 pwm_out1_i_n_4 pwm_out1_i_n_5 pwm_out1_i_n_6 pwm_out1_i_n_7 pwm_out1_i_n_8 pwm_out1_i_n_9 -autobundled netbloc @pwm_out1_i_n_0,pwm_out1_i_n_1 1 14 1 4180 load netBundle @duty 8 duty[7] duty[6] duty[5] duty[4] duty[3] duty[2] duty[1] duty[0] -autobundled netbloc @duty 1 0 1 20J load netBundle @half_duty_new4_i_n_0 31 half_duty_new4_i_n_0 half_duty_new4_i_n_1 half_duty_new4_i_n_2 half_duty_new4_i_n_3 half_duty_new4_i_n_4 half_duty_new4_i_n_5 half_duty_new4_i_n_6 half_duty_new4_i_n_7 half_duty_new4_i_n_8 half_duty_new4_i_n_9 half_duty_new4_i_n_10 half_duty_new4_i_n_11 half_duty_new4_i_n_12 half_duty_new4_i_n_13 half_duty_new4_i_n_14 half_duty_new4_i_n_15 half_duty_new4_i_n_16 half_duty_new4_i_n_17 half_duty_new4_i_n_18 half_duty_new4_i_n_19 half_duty_new4_i_n_20 half_duty_new4_i_n_21 half_duty_new4_i_n_22 half_duty_new4_i_n_23 half_duty_new4_i_n_24 half_duty_new4_i_n_25 half_duty_new4_i_n_26 half_duty_new4_i_n_27 half_duty_new4_i_n_28 half_duty_new4_i_n_29 half_duty_new4_i_n_30 -autobundled netbloc @half_duty_new4_i_n_0 1 4 2 1260 370 1530 load netBundle @count_1 9 count[0]0[8] count[0]0[7] count[0]0[6] count[0]0[5] count[0]0[4] count[0]0[3] count[0]0[2] count[0]0[1] count[0]0[0] -autobundled netbloc @count_1 1 8 1 NJ load netBundle @count 9 count[0][8] count[0][7] count[0][6] count[0][5] count[0][4] count[0][3] count[0][2] count[0][1] count[0][0] -autobundled netbloc @count 1 9 1 2710 load netBundle @half_duty_new 8 half_duty_new[7] half_duty_new[6] half_duty_new[5] half_duty_new[4] half_duty_new[3] half_duty_new[2] half_duty_new[1] half_duty_new[0] -autobundled netbloc @half_duty_new 1 12 1 3630 load netBundle @half_duty_new0 8 half_duty_new0[7] half_duty_new0[6] half_duty_new0[5] half_duty_new0[4] half_duty_new0[3] half_duty_new0[2] half_duty_new0[1] half_duty_new0[0] -autobundled netbloc @half_duty_new0 1 11 1 3350 load netBundle @half_duty_new1 8 half_duty_new1[7] half_duty_new1[6] half_duty_new1[5] half_duty_new1[4] half_duty_new1[3] half_duty_new1[2] half_duty_new1[1] half_duty_new1[0] -autobundled netbloc @half_duty_new1 1 10 1 3100 load netBundle @count_reg 9 count_reg[0]__0[8] count_reg[0]__0[7] count_reg[0]__0[6] count_reg[0]__0[5] count_reg[0]__0[4] count_reg[0]__0[3] count_reg[0]__0[2] count_reg[0]__0[1] count_reg[0]__0[0] -autobundled netbloc @count_reg 1 7 8 2080 120 NJ N NJ 120 3080 260 NJ 260 NJ 260 NJ 260 4220 load netBundle @half_duty_new2 31 half_duty_new2[30] half_duty_new2[29] half_duty_new2[28] half_duty_new2[27] half_duty_new2[26] half_duty_new2[25] half_duty_new2[24] half_duty_new2[23] half_duty_new2[22] half_duty_new2[21] half_duty_new2[20] half_duty_new2[19] half_duty_new2[18] half_duty_new2[17] half_duty_new2[16] half_duty_new2[15] half_duty_new2[14] half_duty_new2[13] half_duty_new2[12] half_duty_new2[11] half_duty_new2[10] half_duty_new2[9] half_duty_new2[8] half_duty_new2[7] half_duty_new2[6] half_duty_new2[5] half_duty_new2[4] half_duty_new2[3] half_duty_new2[2] half_duty_new2[1] half_duty_new2[0] -autobundled netbloc @half_duty_new2 1 8 1 2360 load netBundle @half_duty_new3 31 half_duty_new3[30] half_duty_new3[29] half_duty_new3[28] half_duty_new3[27] half_duty_new3[26] half_duty_new3[25] half_duty_new3[24] half_duty_new3[23] half_duty_new3[22] half_duty_new3[21] half_duty_new3[20] half_duty_new3[19] half_duty_new3[18] half_duty_new3[17] half_duty_new3[16] half_duty_new3[15] half_duty_new3[14] half_duty_new3[13] half_duty_new3[12] half_duty_new3[11] half_duty_new3[10] half_duty_new3[9] half_duty_new3[8] half_duty_new3[7] half_duty_new3[6] half_duty_new3[5] half_duty_new3[4] half_duty_new3[3] half_duty_new3[2] half_duty_new3[1] half_duty_new3[0] -autobundled netbloc @half_duty_new3 1 7 1 2080 load netBundle @half_duty_new4 32 half_duty_new4[31] half_duty_new4[30] half_duty_new4[29] half_duty_new4[28] half_duty_new4[27] half_duty_new4[26] half_duty_new4[25] half_duty_new4[24] half_duty_new4[23] half_duty_new4[22] half_duty_new4[21] half_duty_new4[20] half_duty_new4[19] half_duty_new4[18] half_duty_new4[17] half_duty_new4[16] half_duty_new4[15] half_duty_new4[14] half_duty_new4[13] half_duty_new4[12] half_duty_new4[11] half_duty_new4[10] half_duty_new4[9] half_duty_new4[8] half_duty_new4[7] half_duty_new4[6] half_duty_new4[5] half_duty_new4[4] half_duty_new4[3] half_duty_new4[2] half_duty_new4[1] half_duty_new4[0] -autobundled netbloc @half_duty_new4 1 5 1 1550 load netBundle @half_duty_new5 31 half_duty_new5[30] half_duty_new5[29] half_duty_new5[28] half_duty_new5[27] half_duty_new5[26] half_duty_new5[25] half_duty_new5[24] half_duty_new5[23] half_duty_new5[22] half_duty_new5[21] half_duty_new5[20] half_duty_new5[19] half_duty_new5[18] half_duty_new5[17] half_duty_new5[16] half_duty_new5[15] half_duty_new5[14] half_duty_new5[13] half_duty_new5[12] half_duty_new5[11] half_duty_new5[10] half_duty_new5[9] half_duty_new5[8] half_duty_new5[7] half_duty_new5[6] half_duty_new5[5] half_duty_new5[4] half_duty_new5[3] half_duty_new5[2] half_duty_new5[1] half_duty_new5[0] -autobundled netbloc @half_duty_new5 1 3 1 940 levelinfo -pg 1 0 220 470 810 1090 1340 1680 1890 2230 2540 2850 3220 3490 3740 4050 4320 4630 4880 5070 -top 0 -bot 690 show zoom 0.261122 scrollpos -4 -30 # # initialize ictrl to current module pwm work:pwm:NOFILE ictrl init topinfo | ictrl layer glayer install ictrl layer glayer config ibundle 1 ictrl layer glayer config nbundle 0 ictrl layer glayer config pbundle 0 ictrl layer glayer config cache 1