---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 06/02/2018 08:07:20 PM -- Design Name: -- Module Name: MAIN - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity MAIN is Port ( clk : in STD_LOGIC; led : out std_logic; btnc : in std_logic; btnu : in STD_LOGIC; btnd : in STD_LOGIC; sled : out std_logic; an : out STD_LOGIC_vector(3 downto 0); seg : out STD_LOGIC_vector(7 downto 0); onoff : in std_logic; sw : in std_logic_vector(7 downto 0); gain, enable, output : out std_logic); end MAIN; architecture Behavioral of MAIN is component divider is Port(dividend : in std_logic_vector(7 downto 0); quotient : out integer); end component; component octave is Port(btnc,clk : in std_logic; oct : out std_logic_vector(1 downto 0)); end component; component freqGen is Port(sw : in std_logic_vector(7 downto 0); oct : in std_logic_vector(1 downto 0); freq : out integer); end component; component freqToSound is Port(freq : in integer; clk : in std_logic; output : out std_logic); end component; component bpmcreator is Port(truebpm : in integer; sled : out std_logic; enable : out std_logic; clk : in std_logic); end component; component bpm is Port(btnu, btnd, clk : in std_logic; countOut : out std_logic_vector(7 downto 0)); end component; component sseg_dec is Port(sign,valid,clk : in std_logic; ALU_VAL : in std_logic_vector(7 downto 0); DISP_EN : out std_logic_vector(3 downto 0); SEGMENTS : out std_logic_vector(7 downto 0)); end component; signal count : std_logic_vector(7 downto 0); signal oct : std_logic_vector(1 downto 0); signal freq : integer; signal truebpm : integer; signal bpmPulse : std_logic; signal tmp : std_logic; begin octav: octave Port map(btnc => btnc, clk => clk, oct => oct); fg: freqGen Port map(sw => sw, oct => oct, freq => freq); f2s: freqToSound Port map(freq => freq, clk => clk, output => output); bpmcr : bpmcreator Port map(clk => clk, sled => sled, truebpm => truebpm, enable => bpmPulse); bpm1: bpm Port map(btnu => btnu, btnd => btnd, clk => clk, countOut => count); div: divider Port map(dividend => count, quotient => truebpm); sseg : sseg_dec Port map(sign => '0', valid => '1', clk => clk, ALU_VAL => count, DISP_EN => an, SEGMENTS => seg); enable <= onoff or bpmPulse; led <= onoff or bpmPulse; gain <= '1'; end Behavioral;