MazeArray Project Status
Project File: MazeGame.xise Parser Errors: No Errors
Module Name: MazeArray Implementation State: Programming File Generated
Target Device: xc6slx16-3csg324
  • Errors:
No Errors
Product Version:ISE 14.5
  • Warnings:
10 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 332 18,224 1%  
    Number used as Flip Flops 332      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 837 9,112 9%  
    Number used as logic 827 9,112 9%  
        Number using O6 output only 464      
        Number using O5 output only 300      
        Number using O5 and O6 63      
        Number used as ROM 0      
    Number used as Memory 0 2,176 0%  
    Number used exclusively as route-thrus 10      
        Number with same-slice register load 0      
        Number with same-slice carry load 10      
        Number with other load 0      
Number of occupied Slices 291 2,278 12%  
Number of MUXCYs used 340 4,556 7%  
Number of LUT Flip Flop pairs used 841      
    Number with an unused Flip Flop 511 841 60%  
    Number with an unused LUT 4 841 1%  
    Number of fully used LUT-FF pairs 326 841 38%  
    Number of unique control sets 19      
    Number of slice register sites lost
        to control set restrictions
60 18,224 1%  
Number of bonded IOBs 56 232 24%  
    Number of LOCed IOBs 54 56 96%  
Number of RAMB16BWERs 0 32 0%  
Number of RAMB8BWERs 0 64 0%  
Number of BUFIO2/BUFIO2_2CLKs 0 32 0%  
Number of BUFIO2FB/BUFIO2FB_2CLKs 0 32 0%  
Number of BUFG/BUFGMUXs 3 16 18%  
    Number used as BUFGs 3      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 0 4 0%  
Number of ILOGIC2/ISERDES2s 0 248 0%  
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 248 0%  
Number of OLOGIC2/OSERDES2s 0 248 0%  
Number of BSCANs 0 4 0%  
Number of BUFHs 0 128 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 32 0%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 0 2 0%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 3.70      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentFri Dec 5 11:38:16 201408 Warnings (0 new)11 Infos (0 new)
Translation ReportCurrentFri Dec 5 11:38:26 2014000
Map ReportCurrentFri Dec 5 11:38:56 201402 Warnings (0 new)7 Infos (0 new)
Place and Route ReportCurrentFri Dec 5 11:39:12 2014003 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentFri Dec 5 11:39:20 2014004 Infos (0 new)
Bitgen ReportCurrentFri Dec 5 11:39:32 2014000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentFri Dec 5 11:39:34 2014
WebTalk Log FileCurrentFri Dec 5 11:39:40 2014

Date Generated: 12/05/2014 - 14:59:22