Project Statistics |
PROP_Enable_Message_Filtering=false |
PROP_FitterReportFormat=HTML |
PROP_LastAppliedGoal=Balanced |
PROP_LastAppliedStrategy=Xilinx Default (unlocked) |
PROP_ManualCompileOrderImp=false |
PROP_PropSpecInProjFile=Store all values |
PROP_Simulator=ISim (VHDL/Verilog) |
PROP_SynthTopFile=changed |
PROP_Top_Level_Module_Type=HDL |
PROP_UseSmartGuide=false |
PROP_UserConstraintEditorPreference=Text Editor |
PROP_intProjectCreationTimestamp=2014-11-13T10:28:50 |
PROP_intWbtProjectID=C8CA0A06AD2F4347A54F2CE36DE18B7D |
PROP_intWbtProjectIteration=28 |
PROP_intWorkingDirLocWRTProjDir=Same |
PROP_intWorkingDirUsed=No |
PROP_lockPinsUcfFile=changed |
PROP_AutoTop=true |
PROP_DevFamily=Spartan6 |
PROP_ibiswriterOutputFile=sseg_dec |
PROP_DevDevice=xc6slx16 |
PROP_DevFamilyPMName=spartan6 |
PROP_DevPackage=csg324 |
PROP_Synthesis_Tool=XST (VHDL/Verilog) |
PROP_DevSpeed=-3 |
PROP_PreferredLanguage=VHDL |
PROP_netgenPostMapSimModelName=sseg_dec_map.vhd |
PROP_netgenPostParSimModelName=sseg_dec_timesim.vhd |
PROP_netgenPostSynthesisSimModelName=sseg_dec_synthesis.vhd |
PROP_netgenPostXlateSimModelName=sseg_dec_translate.vhd |
PROP_netgenRenameTopLevEntTo=sseg_dec |
FILE_UCF=1 |
FILE_VHDL=6 |