Map_Decoder Project Status (12/02/2014 - 18:41:24)
Project File: FinalProject.xise Parser Errors: No Errors
Module Name: sseg_dec Implementation State: Synthesized
Target Device: xc3s500e-4fg320
  • Errors:
 
Product Version:ISE 14.5
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slices 67 4656 1%
Number of Slice Flip Flops 35 9312 0%
Number of 4 input LUTs 124 9312 1%
Number of bonded IOBs 23 232 9%
Number of GCLKs 1 24 4%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentTue Dec 2 18:37:12 2014   
Translation Report     
Map Report     
Place and Route Report     
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 12/02/2014 - 18:41:25