game Project Status (12/06/2014 - 10:40:37) | |||
Project File: | FinalProject.xise | Parser Errors: | No Errors |
Module Name: | game | Implementation State: | Synthesized |
Target Device: | xc3s500e-4fg320 |
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No Errors |
Product Version: | ISE 14.5 |
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2 Warnings (0 new) |
Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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Device Utilization Summary (estimated values) | [-] | |||
Logic Utilization | Used | Available | Utilization | |
Number of Slices | 167 | 4656 | 3% | |
Number of Slice Flip Flops | 159 | 9312 | 1% | |
Number of 4 input LUTs | 328 | 9312 | 3% | |
Number of bonded IOBs | 48 | 232 | 20% | |
Number of BRAMs | 1 | 20 | 5% | |
Number of GCLKs | 2 | 24 | 8% |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Sat Dec 6 10:40:36 2014 | 0 | 2 Warnings (0 new) | 6 Infos (0 new) | |
Translation Report | Out of Date | Fri Dec 5 13:55:54 2014 | 0 | 0 | 0 | |
Map Report | Out of Date | Fri Dec 5 13:56:02 2014 | 0 | 29 Warnings (0 new) | 3 Infos (0 new) | |
Place and Route Report | Out of Date | Fri Dec 5 13:56:16 2014 | 0 | 5 Warnings (0 new) | 2 Infos (0 new) | |
Power Report | ||||||
Post-PAR Static Timing Report | Out of Date | Fri Dec 5 13:56:18 2014 | 0 | 0 | 6 Infos (0 new) | |
Bitgen Report | Out of Date | Fri Dec 5 13:56:28 2014 | 0 | 29 Warnings (0 new) | 0 |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
ISIM Simulator Log | Out of Date | Fri Dec 5 13:57:26 2014 | |
WebTalk Report | Out of Date | Fri Dec 5 13:56:28 2014 | |
WebTalk Log File | Out of Date | Fri Dec 5 13:56:32 2014 |