Input_FSM Project Status (11/12/2014 - 12:12:16)
Project File: FinalProject.xise Parser Errors: No Errors
Module Name: Input_FSM Implementation State: Synthesized
Target Device: xc3s500e-4fg320
  • Errors:
 
Product Version:ISE 14.5
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment:  
  • Final Timing Score:
  
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
Post-Synthesis Simulation Model ReportOut of DateWed Nov 12 12:06:34 2014
WebTalk ReportOut of DateWed Nov 12 12:07:58 2014
WebTalk Log FileOut of DateWed Nov 12 12:08:02 2014

Date Generated: 11/12/2014 - 12:12:45