game Project Status (12/02/2014 - 19:10:24) | |||
Project File: | FinalProject.xise | Parser Errors: | No Errors |
Module Name: | scroll_clk | Implementation State: | Synthesized |
Target Device: | xc3s500e-4fg320 |
|
|
Product Version: | ISE 14.5 |
|
|
Design Goal: | Balanced |
|
|
Design Strategy: | Xilinx Default (unlocked) |
|
|
Environment: | System Settings |
|
Device Utilization Summary (estimated values) | [-] | |||
Logic Utilization | Used | Available | Utilization | |
Number of Slices | 21 | 4656 | 0% | |
Number of Slice Flip Flops | 33 | 9312 | 0% | |
Number of 4 input LUTs | 41 | 9312 | 0% | |
Number of bonded IOBs | 2 | 232 | 0% | |
Number of GCLKs | 1 | 24 | 4% |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Tue Dec 2 18:51:10 2014 | ||||
Translation Report | ||||||
Map Report | ||||||
Place and Route Report | ||||||
CPLD Fitter Report (Text) | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated |