---------------------------------------------------------------------------------- -- Company: Cal Poly CPE 133 -- Engineer: Lauren Byrne and Christopher Gerdom -- -- Create Date: 21:14:38 12/04/2014 -- Design Name: -- Module Name: vga_line_draw_structual - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity vga_line_draw_structual is Port ( button_in : in STD_LOGIC_VECTOR (3 downto 0); CLK : in STD_LOGIC; RESET : in STD_LOGIC; H_SYNC : out STD_LOGIC; V_SYNC : out STD_LOGIC; R : out STD_LOGIC_VECTOR (2 downto 0); G : out STD_LOGIC_VECTOR (2 downto 0); B : out STD_LOGIC_VECTOR (1 downto 0); GAME_STATE : out STD_LOGIC); end vga_line_draw_structual; architecture Behavioral of vga_line_draw_structual is component game_logic_top_7 is Port ( RESET : in STD_LOGIC; CLKGAME : in STD_LOGIC; CLK100 : in STD_LOGIC; WRITEN : in STD_LOGIC; MOVE : in STD_LOGIC_VECTOR (1 downto 0); DATA_FROM_MEM: in STD_LOGIC_VECTOR(2 downto 0); GAME_STATE : out STD_LOGIC; LOGIC_ADDRESS_OUT : out STD_LOGIC_VECTOR (15 downto 0); WRITE_EN : out STD_LOGIC); end component; COMPONENT vga_controller_640_60 is port( rst : in std_logic; pixel_clk : in std_logic; HS : out std_logic; VS : out std_logic; hcount : out std_logic_vector(10 downto 0); vcount : out std_logic_vector(10 downto 0); blank : out std_logic ); end COMPONENT; COMPONENT game_mem_driver iS Port ( LOGIC_ADDR : in STD_LOGIC_VECTOR (15 downto 0); DISP_ADDR : in STD_LOGIC_VECTOR (15 downto 0); DATA_IN : in STD_LOGIC_VECTOR (2 downto 0); DISPLAY_PRIORITY : in STD_LOGIC; MEM_CLK : in STD_LOGIC; RESET : in STD_LOGIC; WRITE_EN: in STD_LOGIC; --MEMORY OUTPUTS DATA_OUT : out STD_LOGIC_VECTOR (2 downto 0):="000"; WRITEN : out STD_LOGIC:='0'); end COMPONENT; component vga_encoder is Port ( X : in STD_LOGIC_VECTOR (10 downto 0); Y : in STD_LOGIC_VECTOR (10 downto 0); DATA : in STD_LOGIC_VECTOR (2 downto 0); -- RESET: IN STD_LOGIC; BLANKING: IN STD_LOGIC; PRIORITY : out STD_LOGIC; ADDRESS_OUT : out STD_LOGIC_VECTOR (15 downto 0); R : out STD_LOGIC_VECTOR (2 downto 0); G : out STD_LOGIC_VECTOR (2 downto 0); B : out STD_LOGIC_VECTOR (1 downto 0)); end component; component clk_div2 is port( clk: in std_logic; sclk:out std_logic); end component; component CLK_DIV is port (-- Clock in ports CLK : in std_logic; -- Clock out ports CLK100 : out std_logic; CLK25 : out std_logic; CLKGAME : out std_logic ); end component; signal clk100, clkgame,to_clkgame, clk25, write_en,address_taken,blanking,priority : std_logic; signal logic_address_out,display_address: std_logic_vector(15 downto 0); signal data_from_mem: std_logic_vector(2 downto 0); signal move_in : std_logic_vector(1 downto 0); signal x, y : std_logic_vector(10 downto 0); begin move0: game_logic_top_7 port map ( RESET =>RESET, CLKGAME =>clkgame, CLK100 => clk100, WRITEN => address_taken, MOVE => MOVE_IN, DATA_FROM_MEM => data_from_mem, GAME_STATE =>GAME_STATE, LOGIC_ADDRESS_OUT=>logic_address_out ); write_en<='1'; mem0: game_mem_driver port map( LOGIC_ADDR => logic_address_out, DISP_ADDR => display_address, DATA_IN =>"100", DISPLAY_PRIORITY => priority, MEM_CLK =>clk100, RESET =>RESET, WRITE_EN =>write_en, --MEMORY OUTPUTS DATA_OUT =>data_from_mem, WRITEN=> address_taken); vga0: vga_controller_640_60 port map( rst => RESET, pixel_clk =>clk25, HS => H_SYNC, VS =>V_SYNC, hcount => x, vcount => y, blank => blanking); vga1: vga_encoder port map( X => x, Y =>y, DATA => data_from_mem, -- RESET=>RESET, BLANKING =>blanking, PRIORITY => priority, ADDRESS_OUT => display_address, R =>R, G =>G, B=>B); clk0: clk_div port map( clk=>CLK, clk100=> clk100, clk25=> clk25, clkgame=> to_clkgame ); clk1: clk_div2 port map( clk=> to_clkgame, sclk=>clkgame); move_cal0: process(button_in) begin case button_in is when "1000" => move_in <= "00"; when "0100" => move_in <= "01"; when "0010" => move_in <= "10"; when "0001" => move_in <= "11"; when others => move_in <= "01"; end case; end process move_cal0; end Behavioral;