---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 11:47:04 11/24/2014 -- Design Name: -- Module Name: Controller - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity whackamoles is Port ( CLK : in STD_LOGIC; Switches: in std_logic_vector(7 downto 0); reset : in std_logic; showLeds : out std_logic_vector(7 downto 0); anodes : out std_logic_vector(3 downto 0); missled : out std_logic_vector(2 downto 0); segments : out std_logic_vector ( 7 downto 0) ); end whackamoles; architecture Behavioral of whackamoles is component linfeedshift is Port ( Clk : in std_logic; reset : in std_logic; update : in std_logic; moles : out std_logic_vector (7 downto 0)); end component linfeedshift; component Whackandscore is Port ( clk : in std_logic; reset : in std_logic; leds : in std_logic_vector(7 downto 0); switches : in std_logic_vector (7 downto 0); finalscore: out std_logic_vector(7 downto 0); succ : out std_logic_vector (7 downto 0); missled : out std_logic_vector(2 downto 0)); end component Whackandscore; component ledcontroller is port (s1 : in STD_LOGIC; s2 : in STD_LOGIC; s3: in STD_LOGIC; s4: in STD_LOGIC; s5: in STD_LOGIC; s6: in STD_LOGIC; s7: in STD_LOGIC; s8: in STD_LOGIC; clk : in std_logic; reset : in std_logic; ledson : in std_logic_vector(7 downto 0); updates : out std_logic; leds : out std_logic_vector (7 downto 0) ); end component Ledcontroller; component sseg_dec is Port ( ALU_VAL : in std_logic_vector(7 downto 0); SIGN : in std_logic; VALID : in std_logic; CLK : in std_logic; DISP_EN : out std_logic_vector(3 downto 0); SEGMENTS : out std_logic_vector(7 downto 0)); end component sseg_dec; component clk_div2 is Port ( clk : in std_logic; sclk : out std_logic); end component clk_div2; signal sclk : std_logic; signal Leds: std_logic_vector (7 downto 0) := "00000000"; signal ledson: std_logic_vector (7 downto 0) := "00000000"; signal updates: std_logic := '1'; signal succ : std_logic_vector (7 downto 0):= "11111111"; signal finalscores: std_logic_vector(7 downto 0); begin clkdivide : clk_div2 port map ( Clk => Clk, sclk => sclk); rng : linfeedshift port map (Clk => sClk, update => updates, reset => reset, moles => Ledson); leddriver : ledcontroller port map ( s1 => succ(0), s2 => succ(1), s3 => succ(2), s4 => succ(3), s5 => succ(4), s6 => succ(5), s7 => succ(6), s8 => succ(7), reset => reset, clk => sclk, updates => updates, ledson => ledson, leds => leds); process(leds) begin showleds <= leds; end process; whackmoles : whackandscore port map (switches => switches, clk => sclk, leds => leds, reset => reset, succ => succ, missled => missled, finalscore => finalscores); display :sseg_dec port map (alu_val => finalscores, sign => '0', valid => '1', clk => clk, disp_en => anodes, segments => segments); end Behavioral;