LIST p=12F629 LIST r=dec MinBank0RAM EQU 0x20 MaxBank0RAM EQU 0x5F W EQU 0x0000 F EQU 0x0001 NoFuses EQU 0x0000 ProtAll EQU 0x0000 ProtOff EQU 0x0180 ProtCode EQU 0x0100 ProtData EQU 0x0080 FuseAddr EQU 0x2007 IdAddr EQU 0x2000 LPosc EQU 0 XTosc EQU 1 HSosc EQU 2 ExtClkosc EQU 3 IntRCosc EQU 4 IntClkOosc EQU 5 ExtRCosc EQU 6 ExtRClkOosc EQU 7 enMCRL EQU 0x20 disPUT EQU 0x10 enWDT EQU 0x08 Bandgap00 EQU 0x0000 Bandgap01 EQU 0x1000 Bandgap10 EQU 0x2000 Bandgap11 EQU 0x3000 MinBank1RAM EQU 0 MaxBank1RAM EQU 0 MinBank2RAM EQU 0 MaxBank2RAM EQU 0 MinBank3RAM EQU 0 MaxBank3RAM EQU 0 OsccalInitAddr EQU 0x03FF enBoden EQU 0x0040 INDF EQU 0x0000 TMR0 EQU 0x0001 PCL EQU 0x0002 STATUS EQU 0x0003 FSR EQU 0x0004 PORTA EQU 0x0005 GPIO EQU 0x0005 PCLATH EQU 0x000A INTCON EQU 0x000B PIR1 EQU 0x000C TMR1L EQU 0x000E TMR1H EQU 0x000F T1CON EQU 0x0010 CMCON EQU 0x0019 ADRESH EQU 0x001E ADCON0 EQU 0x001F OPTION_REG EQU 0x0001 TRISA EQU 0x0005 TRISIO EQU 0x0005 PIE1 EQU 0x000C PCON EQU 0X000E OSCCAL EQU 0X0010 WPU EQU 0X0015 IOCB EQU 0X0016 IOC EQU 0X0016 VRCON EQU 0X0019 EEDATA EQU 0X001A EEADR EQU 0X001B EECON1 EQU 0X001C EECON2 EQU 0X001D ADRSEL EQU 0X001E ANSEL EQU 0X001F cblock MinBank0RAM W_TEMP STATUS_TEMP FSR_TEMP PCLATH_TEMP DelayCount a BitVar_1 Heap_ endc Heap EQU Heap_ cblock MinBank1RAM endc cblock MinBank2RAM endc cblock MinBank3RAM endc org 0 clrf PCLATH goto initialise org FuseAddr data NoFuses + IntRCosc + Bandgap00 + disPUT + ProtOff org 0x2100 org 0x2000 org 4 bcf PIR1,0 btfsc BitVar_1,0 goto CompilerLabel_83 CompilerLabel_82 bsf BitVar_1,0 goto CompilerLabel_84 CompilerLabel_83 bcf BitVar_1,0 CompilerLabel_84 btfss BitVar_1,0 goto CompilerLabel_92 CompilerLabel_93 goto CompilerLabel_106 CompilerLabel_92 CompilerLabel_106 RETFIE pDelay_4uS CompilerLabel_17 addlw 255 btfss STATUS,2 goto CompilerLabel_17 CompilerLabel_22 return pDelay_mS movwf DelayCount CompilerLabel_31 movf DelayCount,W sublw 0 btfsc STATUS,0 goto CompilerLabel_33 CompilerLabel_32 movlw 255 call pDelay_4uS decf DelayCount,F goto CompilerLabel_31 CompilerLabel_33 return initialise bsf STATUS,5 clrf OPTION_REG bsf OPTION_REG,7 bcf STATUS,5 clrf FSR clrf GPIO clrf intcon movlw 0xFF movwf CMCON clrf T1CON movlw (GPIO | 0x80) movwf FSR movlw 0 movwf INDF movlw 0x8F bsf STATUS,5 movwf OPTION_REG bcf STATUS,5 clrf STATUS bcf T1CON,0 movlw 0x80 movwf TMR1H clrf TMR1L clrf INTCON movlw (PIE1 | 0x080) movwf FSR movlw 1 movwf INDF clrf PIR1 bsf INTCON,6 bsf INTCON,7 movlw 0x0E movwf T1CON bsf T1CON,0 movlw 7 movwf CMCON bcf GPIO,1 bcf GPIO,2 mainloop Sleep goto mainloop tim1 EQU 70 org 0x800 org 0x1000 org 0x1800 END