--Uses 4-bit ripple carry adder to add 3 to a number if it is greater then 5
--@author Sam Malicoat, Ryan Kendall

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Add3 is
            Port ( input : in STD_LOGIC_VECTOR (3 downto 0);
                   output : out STD_LOGIC_VECTOR (3 downto 0));
end Add3;

architecture Behavioral of Add3 is
component Full_Adder
            Port(  A: in STD_LOGIC_VECTOR(3 downto 0);
                   B: in STD_LOGIC_VECTOR(3 downto 0);
                   Result: out STD_LOGIC_VECTOR(3 downto 0));
end component;

Signal addTo: STD_LOGIC_VECTOR(3 downto 0);

begin

Adder : Full_Adder port map(
            A=>input,
            B=>addTo,
            Result=>output);


process (input) is
begin

if ((input(3)='1' or input(2)='1') and (input(1)='1' or input(0)='1')) then
        addTo<="0011";
else
        addTo<="0000";
end if;
end process;


end Behavioral;