--Converts a Hex input to a 3 digit decimal value 
--@author Sam Malicoat, Ryan Kendall

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity ConvertHex2Dec is
    Port ( Hex : in STD_LOGIC_VECTOR (6 downto 0);
           Dec : out STD_LOGIC_VECTOR (11 downto 0));
end ConvertHex2Dec;

architecture Behavioral of ConvertHex2Dec is

component Add3_3Times Port ( Input : in STD_LOGIC_VECTOR (11 downto 0);
       Output : out STD_LOGIC_VECTOR (11 downto 0));
end component;

Signal connect1_0,connect1_2,connect2_1, connect2_3,connect3_2, connect3_4,connect4_3, connect4_5,connect5_4,connect5_6,connect6_5,connect6_7,connect7_6,connect7_8,connect8_7,connect8_9: STD_LOGIC_VECTOR(11 downto 0);

begin

connect1_0<="000000000000";

shift1: Add3_3Times port map(
        Input=>connect1_0,
        Output=>connect1_2);
        
        connect2_1<=connect1_2(10 downto 0)&'0';
        
shift2: Add3_3Times port map(
        Input=>(connect2_1),
        Output=>connect2_3);
        
        connect3_2<=connect2_3(10 downto 0)&Hex(6);
        
shift3: Add3_3Times port map(
        Input=>(connect3_2),
        Output=>connect3_4);       
        
        connect4_3<=connect3_4(10 downto 0)&Hex(5);
        
shift4: Add3_3Times port map(
        Input=>(connect4_3),
        Output=>connect4_5);
        
        connect5_4<=connect4_5(10 downto 0)&Hex(4);
        
shift5: Add3_3Times port map(
        Input=>(connect5_4),
        Output=>connect5_6);
        
        connect6_5<=connect5_6(10 downto 0)&Hex(3);
        
shift6: Add3_3Times port map(
        Input=>(connect6_5),
        Output=>connect6_7);
        
        connect7_6<=connect6_7(10 downto 0)&Hex(2);
        
shift7: Add3_3Times port map(
        Input=>(connect7_6),
        Output=>connect7_8);
            
        connect8_7<=connect7_8(10 downto 0)&Hex(1);
        
shift8: Add3_3Times port map(
        Input=>(connect8_7),
        Output=>connect8_9);    
        
        Dec<=connect8_9(10 downto 0)&Hex(0);


end Behavioral;