---------------------------------------------------------------------------------- -- Engineer: Ryan Schouten -- -- Create Date: 09/29/2016 02:16:27 PM -- Design Name: Half-adder -- Module Name: half_adder - Behavioral -- Project Name: Lab 1 -- Target Devices: basys3 -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity half_adder is Port ( a : in STD_LOGIC; b : in STD_LOGIC; y : out STD_LOGIC; --Sum x : out STD_LOGIC); --Carryout end half_adder; architecture Behavioral of half_adder is begin y <= (NOT(a) and b) OR (NOT(B) AND A); x <= A AND B; end Behavioral;