`timescale 1ns / 1ps module ultrasonic_driver( input CLK, input ECHO, output TRIG, output [31:0]RF); // intermediate signals logic trig_d; logic echo_d; logic [31:0]data_d; logic [31:0]trig_cnt; logic [31:0]echo_cnt; // trigger signal generator always @ (posedge CLK) begin if (trig_cnt < 'd100_000) begin trig_d = 'd1; trig_cnt = trig_cnt + 'd1; end else if (trig_cnt < 'd9_900_000) begin trig_d = 'd0; trig_cnt = trig_cnt + 'd1; end else begin trig_cnt = 'd0; end end // echo signal reciever always @ (posedge CLK) begin if (ECHO & !echo_d) begin echo_cnt = 'd0; end else if (ECHO & echo_d) begin echo_cnt = echo_cnt + 'd1; end else if (!ECHO & echo_d) begin data_d = echo_cnt; end echo_d = ECHO; end // output assignment assign TRIG = trig_d; assign RF = data_d; endmodule