---------------------------------------------------------------------------------- -- Company: Ratner Engineering -- Engineer: bryan mealy -- -- Create Date: 15:27:40 12/27/2010 -- Design Name: -- Module Name: clk_div.vhd -- Project Name: -- Target Devices: -- Tool versions: -- Description: This divides the input clock frequency into a slower -- frequency. The frequency is set by the the MAX_COUNT -- constant in the declarative region of the architecture. -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -------------------------------------------------------------------------------- ----------------------------------------------------------------------- ----------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ----------------------------------------------------------------------- -- Module to divide the clock ----------------------------------------------------------------------- entity clk_div2_1 is Port ( clk_1 : in std_logic; sclk_1 : out std_logic); end clk_div2_1; architecture my_clk_div_1 of clk_div2_1 is constant max_count_1 : integer := (50000000); signal tmp_clk_1 : std_logic := '0'; begin my_div_1: process (clk_1,tmp_clk_1) variable div_cnt_1 : integer := 0; begin if (rising_edge(clk_1)) then if (div_cnt_1 = MAX_COUNT_1) then tmp_clk_1 <= not tmp_clk_1; div_cnt_1 := 0; else div_cnt_1 := div_cnt_1 + 1; end if; end if; sclk_1 <= tmp_clk_1; end process my_div_1; end my_clk_div_1;