Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click here.

software_version_and_target_device
betaFALSE build_version1909853
date_generatedMon Nov 6 20:15:16 2017 os_platformWIN64
product_versionVivado v2017.2 (64-bit) project_id910a2cfe7f854ad9923e9b519533335d
project_iteration1 random_idc855ab60bf965d389f57cce4a48a718d
registration_idc855ab60bf965d389f57cce4a48a718d route_designTRUE
target_devicexc7z010 target_familyzynq
target_packageclg400 target_speed-1
tool_flowVivado

user_environment
cpu_nameIntel(R) Core(TM) i5-5287U CPU @ 2.90GHz cpu_speed2900 MHz
os_nameMicrosoft Windows 8 or later , 64-bit os_releasemajor release (build 9200)
system_ram6.000 GB total_processors1

vivado_usage
java_command_handlers
addsources=1 autoconnectport=2 createblockdesign=1 createtophdl=1
customizersbblock=1 editproperties=1 newproject=1 regeneratersblayout=1
runbitgen=1
other_data
guimode=1
project_data
constraintsetcount=1 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=0 export_simulation_ies=0
export_simulation_modelsim=0 export_simulation_questa=0 export_simulation_riviera=0 export_simulation_vcs=0
export_simulation_xsim=0 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=0 simulator_language=Mixed srcsetcount=2 synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilog target_simulator=XSim totalimplruns=7 totalsynthesisruns=7

unisim_transformation
post_unisim_transformation
bibuf=130 bufg=1 carry4=114 fdre=1196
fdse=52 gnd=117 lut1=169 lut2=199
lut3=429 lut4=303 lut5=144 lut6=275
muxf7=4 obuf=2 ps7=1 srl16e=19
srlc32e=47 vcc=59
pre_unisim_transformation
bibuf=130 bufg=1 carry4=114 fdre=1196
fdse=52 gnd=117 lut1=169 lut2=199
lut3=429 lut4=303 lut5=144 lut6=275
muxf7=4 obuf=2 ps7=1 srl16e=19
srlc32e=47 vcc=59

ip_statistics
IP_Integrator/1
bdsource=USER core_container=NA da_axi4_cnt=2 da_ps7_cnt=1
iptotal=1 maxhierdepth=0 numblks=10 numhdlrefblks=0
numhierblks=4 numhlsblks=0 numnonxlnxblks=0 numpkgbdblks=0
numreposblks=6 numsysgenblks=0 synth_mode=OOC_per_IP x_iplanguage=VERILOG
x_iplibrary=BlockDiagram x_ipname=design_1 x_ipvendor=xilinx.com x_ipversion=1.00.a
axi_crossbar_v2_1_14_axi_crossbar/1
c_axi_addr_width=32 c_axi_aruser_width=1 c_axi_awuser_width=1 c_axi_buser_width=1
c_axi_data_width=32 c_axi_id_width=1 c_axi_protocol=2 c_axi_ruser_width=1
c_axi_supports_user_signals=0 c_axi_wuser_width=1 c_connectivity_mode=0 c_family=zynq
c_m_axi_addr_width=0x0000001000000010 c_m_axi_base_addr=0x00000000428100000000000042800000 c_m_axi_read_connectivity=0xFFFFFFFFFFFFFFFF c_m_axi_read_issuing=0x0000000100000001
c_m_axi_secure=0x00000000 c_m_axi_write_connectivity=0xFFFFFFFFFFFFFFFF c_m_axi_write_issuing=0x0000000100000001 c_num_addr_ranges=1
c_num_master_slots=2 c_num_slave_slots=1 c_r_register=1 c_s_axi_arb_priority=0x00000000
c_s_axi_base_id=0x00000000 c_s_axi_read_acceptance=0x00000001 c_s_axi_single_thread=0x00000001 c_s_axi_thread_id_width=0x00000000
c_s_axi_write_acceptance=0x00000001 core_container=NA iptotal=1 x_ipcorerevision=14
x_iplanguage=VERILOG x_iplibrary=ip x_ipname=axi_crossbar x_ipproduct=Vivado 2017.2
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=2.1
axi_protocol_converter_v2_1_13_axi_protocol_converter/1
c_axi_addr_width=32 c_axi_aruser_width=1 c_axi_awuser_width=1 c_axi_buser_width=1
c_axi_data_width=32 c_axi_id_width=12 c_axi_ruser_width=1 c_axi_supports_read=1
c_axi_supports_user_signals=0 c_axi_supports_write=1 c_axi_wuser_width=1 c_family=zynq
c_ignore_id=0 c_m_axi_protocol=2 c_s_axi_protocol=1 c_translation_mode=2
core_container=NA iptotal=1 x_ipcorerevision=13 x_iplanguage=VERILOG
x_iplibrary=ip x_ipname=axi_protocol_converter x_ipproduct=Vivado 2017.2 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=2.1
axi_timer/1
c_count_width=32 c_family=zynq c_gen0_assert=1 c_gen1_assert=1
c_one_timer_only=0 c_s_axi_addr_width=5 c_s_axi_data_width=32 c_trig0_assert=1
c_trig1_assert=1 core_container=NA iptotal=1 x_ipcorerevision=15
x_iplanguage=VERILOG x_iplibrary=ip x_ipname=axi_timer x_ipproduct=Vivado 2017.2
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=2.0
axi_timer/2
c_count_width=32 c_family=zynq c_gen0_assert=1 c_gen1_assert=1
c_one_timer_only=0 c_s_axi_addr_width=5 c_s_axi_data_width=32 c_trig0_assert=1
c_trig1_assert=1 core_container=NA iptotal=1 x_ipcorerevision=15
x_iplanguage=VERILOG x_iplibrary=ip x_ipname=axi_timer x_ipproduct=Vivado 2017.2
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=2.0
proc_sys_reset/1
c_aux_reset_high=0 c_aux_rst_width=4 c_ext_reset_high=0 c_ext_rst_width=4
c_family=zynq c_num_bus_rst=1 c_num_interconnect_aresetn=1 c_num_perp_aresetn=1
c_num_perp_rst=1 core_container=NA iptotal=1 x_ipcorerevision=11
x_iplanguage=VERILOG x_iplibrary=ip x_ipname=proc_sys_reset x_ipproduct=Vivado 2017.2
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=5.0
processing_system7_v5.5_user_configuration/1
core_container=NA iptotal=1 pcw_apu_clk_ratio_enable=6:2:1 pcw_apu_peripheral_freqmhz=650
pcw_armpll_ctrl_fbdiv=26 pcw_can0_grp_clk_enable=0 pcw_can0_peripheral_clksrc=External pcw_can0_peripheral_enable=0
pcw_can0_peripheral_freqmhz=-1 pcw_can1_grp_clk_enable=0 pcw_can1_peripheral_clksrc=External pcw_can1_peripheral_enable=0
pcw_can1_peripheral_freqmhz=-1 pcw_can_peripheral_clksrc=IO PLL pcw_can_peripheral_freqmhz=100 pcw_cpu_cpu_pll_freqmhz=1300.000
pcw_cpu_peripheral_clksrc=ARM PLL pcw_crystal_peripheral_freqmhz=50.000000 pcw_dci_peripheral_clksrc=DDR PLL pcw_dci_peripheral_freqmhz=10.159
pcw_ddr_ddr_pll_freqmhz=1050.000 pcw_ddr_hpr_to_critical_priority_level=15 pcw_ddr_hprlpr_queue_partition=HPR(0)/LPR(32) pcw_ddr_lpr_to_critical_priority_level=2
pcw_ddr_peripheral_clksrc=DDR PLL pcw_ddr_port0_hpr_enable=0 pcw_ddr_port1_hpr_enable=0 pcw_ddr_port2_hpr_enable=0
pcw_ddr_port3_hpr_enable=0 pcw_ddr_write_to_critical_priority_level=2 pcw_ddrpll_ctrl_fbdiv=21 pcw_enet0_enet0_io=MIO 16 .. 27
pcw_enet0_grp_mdio_enable=1 pcw_enet0_peripheral_clksrc=IO PLL pcw_enet0_peripheral_enable=1 pcw_enet0_peripheral_freqmhz=1000 Mbps
pcw_enet0_reset_enable=0 pcw_enet1_grp_mdio_enable=0 pcw_enet1_peripheral_clksrc=IO PLL pcw_enet1_peripheral_enable=0
pcw_enet1_peripheral_freqmhz=1000 Mbps pcw_enet1_reset_enable=0 pcw_enet_reset_polarity=Active Low pcw_fclk0_peripheral_clksrc=IO PLL
pcw_fclk1_peripheral_clksrc=IO PLL pcw_fclk2_peripheral_clksrc=IO PLL pcw_fclk3_peripheral_clksrc=IO PLL pcw_fpga0_peripheral_freqmhz=100
pcw_fpga1_peripheral_freqmhz=50 pcw_fpga2_peripheral_freqmhz=50 pcw_fpga3_peripheral_freqmhz=50 pcw_fpga_fclk0_enable=1
pcw_fpga_fclk1_enable=0 pcw_fpga_fclk2_enable=0 pcw_fpga_fclk3_enable=0 pcw_ftm_cti_in0=DISABLED
pcw_ftm_cti_in1=DISABLED pcw_ftm_cti_in2=DISABLED pcw_ftm_cti_in3=DISABLED pcw_ftm_cti_out0=DISABLED
pcw_ftm_cti_out1=DISABLED pcw_ftm_cti_out2=DISABLED pcw_ftm_cti_out3=DISABLED pcw_gpio_emio_gpio_enable=0
pcw_gpio_mio_gpio_enable=1 pcw_gpio_mio_gpio_io=MIO pcw_gpio_peripheral_enable=0 pcw_i2c0_grp_int_enable=0
pcw_i2c0_peripheral_enable=0 pcw_i2c0_reset_enable=0 pcw_i2c1_grp_int_enable=0 pcw_i2c1_peripheral_enable=0
pcw_i2c1_reset_enable=0 pcw_i2c_reset_polarity=Active Low pcw_io_io_pll_freqmhz=1000.000 pcw_iopll_ctrl_fbdiv=20
pcw_irq_f2p_mode=DIRECT pcw_m_axi_gp0_freqmhz=100 pcw_m_axi_gp1_freqmhz=10 pcw_nand_cycles_t_ar=1
pcw_nand_cycles_t_clr=1 pcw_nand_cycles_t_rc=11 pcw_nand_cycles_t_rea=1 pcw_nand_cycles_t_rr=1
pcw_nand_cycles_t_wc=11 pcw_nand_cycles_t_wp=1 pcw_nand_grp_d8_enable=0 pcw_nand_peripheral_enable=0
pcw_nor_cs0_t_ceoe=1 pcw_nor_cs0_t_pc=1 pcw_nor_cs0_t_rc=11 pcw_nor_cs0_t_tr=1
pcw_nor_cs0_t_wc=11 pcw_nor_cs0_t_wp=1 pcw_nor_cs0_we_time=0 pcw_nor_cs1_t_ceoe=1
pcw_nor_cs1_t_pc=1 pcw_nor_cs1_t_rc=11 pcw_nor_cs1_t_tr=1 pcw_nor_cs1_t_wc=11
pcw_nor_cs1_t_wp=1 pcw_nor_cs1_we_time=0 pcw_nor_grp_a25_enable=0 pcw_nor_grp_cs0_enable=0
pcw_nor_grp_cs1_enable=0 pcw_nor_grp_sram_cs0_enable=0 pcw_nor_grp_sram_cs1_enable=0 pcw_nor_grp_sram_int_enable=0
pcw_nor_peripheral_enable=0 pcw_nor_sram_cs0_t_ceoe=1 pcw_nor_sram_cs0_t_pc=1 pcw_nor_sram_cs0_t_rc=11
pcw_nor_sram_cs0_t_tr=1 pcw_nor_sram_cs0_t_wc=11 pcw_nor_sram_cs0_t_wp=1 pcw_nor_sram_cs0_we_time=0
pcw_nor_sram_cs1_t_ceoe=1 pcw_nor_sram_cs1_t_pc=1 pcw_nor_sram_cs1_t_rc=11 pcw_nor_sram_cs1_t_tr=1
pcw_nor_sram_cs1_t_wc=11 pcw_nor_sram_cs1_t_wp=1 pcw_nor_sram_cs1_we_time=0 pcw_override_basic_clock=0
pcw_pcap_peripheral_clksrc=IO PLL pcw_pcap_peripheral_freqmhz=200 pcw_pjtag_peripheral_enable=0 pcw_preset_bank0_voltage=LVCMOS 3.3V
pcw_preset_bank1_voltage=LVCMOS 1.8V pcw_qspi_grp_fbclk_enable=1 pcw_qspi_grp_fbclk_io=MIO 8 pcw_qspi_grp_io1_enable=0
pcw_qspi_grp_single_ss_enable=1 pcw_qspi_grp_single_ss_io=MIO 1 .. 6 pcw_qspi_grp_ss1_enable=0 pcw_qspi_internal_highaddress=0xFCFFFFFF
pcw_qspi_peripheral_clksrc=IO PLL pcw_qspi_peripheral_enable=1 pcw_qspi_peripheral_freqmhz=200 pcw_qspi_qspi_io=MIO 1 .. 6
pcw_s_axi_acp_freqmhz=10 pcw_s_axi_gp0_freqmhz=10 pcw_s_axi_gp1_freqmhz=10 pcw_s_axi_hp0_data_width=64
pcw_s_axi_hp0_freqmhz=10 pcw_s_axi_hp1_data_width=64 pcw_s_axi_hp1_freqmhz=10 pcw_s_axi_hp2_data_width=64
pcw_s_axi_hp2_freqmhz=10 pcw_s_axi_hp3_data_width=64 pcw_s_axi_hp3_freqmhz=10 pcw_sd0_grp_cd_enable=1
pcw_sd0_grp_cd_io=MIO 47 pcw_sd0_grp_pow_enable=0 pcw_sd0_grp_wp_enable=1 pcw_sd0_grp_wp_io=EMIO
pcw_sd0_peripheral_enable=1 pcw_sd0_sd0_io=MIO 40 .. 45 pcw_sd1_grp_cd_enable=0 pcw_sd1_grp_pow_enable=0
pcw_sd1_grp_wp_enable=0 pcw_sd1_peripheral_enable=0 pcw_sdio_peripheral_clksrc=IO PLL pcw_sdio_peripheral_freqmhz=50
pcw_smc_peripheral_clksrc=IO PLL pcw_smc_peripheral_freqmhz=100 pcw_spi0_grp_ss0_enable=0 pcw_spi0_grp_ss1_enable=0
pcw_spi0_grp_ss2_enable=0 pcw_spi0_peripheral_enable=0 pcw_spi1_grp_ss0_enable=0 pcw_spi1_grp_ss1_enable=0
pcw_spi1_grp_ss2_enable=0 pcw_spi1_peripheral_enable=0 pcw_spi_peripheral_clksrc=IO PLL pcw_spi_peripheral_freqmhz=166.666666
pcw_tpiu_peripheral_clksrc=External pcw_tpiu_peripheral_freqmhz=200 pcw_trace_grp_16bit_enable=0 pcw_trace_grp_2bit_enable=0
pcw_trace_grp_32bit_enable=0 pcw_trace_grp_4bit_enable=0 pcw_trace_grp_8bit_enable=0 pcw_trace_peripheral_enable=0
pcw_ttc0_clk0_peripheral_clksrc=CPU_1X pcw_ttc0_clk0_peripheral_freqmhz=133.333333 pcw_ttc0_clk1_peripheral_clksrc=CPU_1X pcw_ttc0_clk1_peripheral_freqmhz=133.333333
pcw_ttc0_clk2_peripheral_clksrc=CPU_1X pcw_ttc0_clk2_peripheral_freqmhz=133.333333 pcw_ttc0_peripheral_enable=1 pcw_ttc0_ttc0_io=EMIO
pcw_ttc1_clk0_peripheral_clksrc=CPU_1X pcw_ttc1_clk0_peripheral_freqmhz=133.333333 pcw_ttc1_clk1_peripheral_clksrc=CPU_1X pcw_ttc1_clk1_peripheral_freqmhz=133.333333
pcw_ttc1_clk2_peripheral_clksrc=CPU_1X pcw_ttc1_clk2_peripheral_freqmhz=133.333333 pcw_ttc1_peripheral_enable=0 pcw_ttc_peripheral_freqmhz=50
pcw_uart0_baud_rate=115200 pcw_uart0_grp_full_enable=0 pcw_uart0_peripheral_enable=0 pcw_uart1_baud_rate=115200
pcw_uart1_grp_full_enable=0 pcw_uart1_peripheral_enable=1 pcw_uart1_uart1_io=MIO 48 .. 49 pcw_uart_peripheral_clksrc=IO PLL
pcw_uart_peripheral_freqmhz=100 pcw_uiparam_ddr_adv_enable=0 pcw_uiparam_ddr_al=0 pcw_uiparam_ddr_bank_addr_count=3
pcw_uiparam_ddr_bl=8 pcw_uiparam_ddr_board_delay0=0.176 pcw_uiparam_ddr_board_delay1=0.159 pcw_uiparam_ddr_board_delay2=0.162
pcw_uiparam_ddr_board_delay3=0.187 pcw_uiparam_ddr_bus_width=32 Bit pcw_uiparam_ddr_cl=7 pcw_uiparam_ddr_clock_0_length_mm=0
pcw_uiparam_ddr_clock_0_package_length=54.563 pcw_uiparam_ddr_clock_0_propogation_delay=160 pcw_uiparam_ddr_clock_1_length_mm=0 pcw_uiparam_ddr_clock_1_package_length=54.563
pcw_uiparam_ddr_clock_1_propogation_delay=160 pcw_uiparam_ddr_clock_2_length_mm=0 pcw_uiparam_ddr_clock_2_package_length=54.563 pcw_uiparam_ddr_clock_2_propogation_delay=160
pcw_uiparam_ddr_clock_3_length_mm=0 pcw_uiparam_ddr_clock_3_package_length=54.563 pcw_uiparam_ddr_clock_3_propogation_delay=160 pcw_uiparam_ddr_clock_stop_en=0
pcw_uiparam_ddr_col_addr_count=10 pcw_uiparam_ddr_cwl=6 pcw_uiparam_ddr_device_capacity=2048 MBits pcw_uiparam_ddr_dq_0_length_mm=0
pcw_uiparam_ddr_dq_0_package_length=104.5365 pcw_uiparam_ddr_dq_0_propogation_delay=160 pcw_uiparam_ddr_dq_1_length_mm=0 pcw_uiparam_ddr_dq_1_package_length=70.676
pcw_uiparam_ddr_dq_1_propogation_delay=160 pcw_uiparam_ddr_dq_2_length_mm=0 pcw_uiparam_ddr_dq_2_package_length=59.1615 pcw_uiparam_ddr_dq_2_propogation_delay=160
pcw_uiparam_ddr_dq_3_length_mm=0 pcw_uiparam_ddr_dq_3_package_length=81.319 pcw_uiparam_ddr_dq_3_propogation_delay=160 pcw_uiparam_ddr_dqs_0_length_mm=0
pcw_uiparam_ddr_dqs_0_package_length=101.239 pcw_uiparam_ddr_dqs_0_propogation_delay=160 pcw_uiparam_ddr_dqs_1_length_mm=0 pcw_uiparam_ddr_dqs_1_package_length=79.5025
pcw_uiparam_ddr_dqs_1_propogation_delay=160 pcw_uiparam_ddr_dqs_2_length_mm=0 pcw_uiparam_ddr_dqs_2_package_length=60.536 pcw_uiparam_ddr_dqs_2_propogation_delay=160
pcw_uiparam_ddr_dqs_3_length_mm=0 pcw_uiparam_ddr_dqs_3_package_length=71.7715 pcw_uiparam_ddr_dqs_3_propogation_delay=160 pcw_uiparam_ddr_dqs_to_clk_delay_0=-0.073
pcw_uiparam_ddr_dqs_to_clk_delay_1=-0.034 pcw_uiparam_ddr_dqs_to_clk_delay_2=-0.03 pcw_uiparam_ddr_dqs_to_clk_delay_3=-0.082 pcw_uiparam_ddr_dram_width=16 Bits
pcw_uiparam_ddr_ecc=Disabled pcw_uiparam_ddr_enable=1 pcw_uiparam_ddr_freq_mhz=525 pcw_uiparam_ddr_high_temp=Normal (0-85)
pcw_uiparam_ddr_memory_type=DDR 3 pcw_uiparam_ddr_partno=MT41K128M16 JT-125 pcw_uiparam_ddr_row_addr_count=14 pcw_uiparam_ddr_speed_bin=DDR3_1066F
pcw_uiparam_ddr_t_faw=40.0 pcw_uiparam_ddr_t_ras_min=35.0 pcw_uiparam_ddr_t_rc=48.75 pcw_uiparam_ddr_t_rcd=7
pcw_uiparam_ddr_t_rp=7 pcw_uiparam_ddr_train_data_eye=1 pcw_uiparam_ddr_train_read_gate=1 pcw_uiparam_ddr_train_write_level=1
pcw_uiparam_ddr_use_internal_vref=0 pcw_usb0_peripheral_enable=1 pcw_usb0_peripheral_freqmhz=60 pcw_usb0_reset_enable=1
pcw_usb0_reset_io=MIO 46 pcw_usb0_usb0_io=MIO 28 .. 39 pcw_usb1_peripheral_enable=0 pcw_usb1_peripheral_freqmhz=60
pcw_usb1_reset_enable=0 pcw_usb_reset_polarity=Active Low pcw_use_cross_trigger=0 pcw_use_m_axi_gp0=1
pcw_use_m_axi_gp1=0 pcw_use_s_axi_acp=0 pcw_use_s_axi_gp0=0 pcw_use_s_axi_gp1=0
pcw_use_s_axi_hp0=0 pcw_use_s_axi_hp1=0 pcw_use_s_axi_hp2=0 pcw_use_s_axi_hp3=0
pcw_wdt_peripheral_clksrc=CPU_1X pcw_wdt_peripheral_enable=0 pcw_wdt_peripheral_freqmhz=133.333333
processing_system7_v5_5_processing_system7/1
c_dm_width=4 c_dq_width=32 c_dqs_width=4 c_emio_gpio_width=64
c_en_emio_enet0=0 c_en_emio_enet1=0 c_en_emio_pjtag=0 c_en_emio_trace=0
c_fclk_clk0_buf=TRUE c_fclk_clk1_buf=FALSE c_fclk_clk2_buf=FALSE c_fclk_clk3_buf=FALSE
c_gp0_en_modifiable_txn=1 c_gp1_en_modifiable_txn=1 c_include_acp_trans_check=0 c_include_trace_buffer=0
c_irq_f2p_mode=DIRECT c_m_axi_gp0_enable_static_remap=0 c_m_axi_gp0_id_width=12 c_m_axi_gp0_thread_id_width=12
c_m_axi_gp1_enable_static_remap=0 c_m_axi_gp1_id_width=12 c_m_axi_gp1_thread_id_width=12 c_mio_primitive=54
c_num_f2p_intr_inputs=1 c_package_name=clg400 c_ps7_si_rev=PRODUCTION c_s_axi_acp_aruser_val=31
c_s_axi_acp_awuser_val=31 c_s_axi_acp_id_width=3 c_s_axi_gp0_id_width=6 c_s_axi_gp1_id_width=6
c_s_axi_hp0_data_width=64 c_s_axi_hp0_id_width=6 c_s_axi_hp1_data_width=64 c_s_axi_hp1_id_width=6
c_s_axi_hp2_data_width=64 c_s_axi_hp2_id_width=6 c_s_axi_hp3_data_width=64 c_s_axi_hp3_id_width=6
c_trace_buffer_clock_delay=12 c_trace_buffer_fifo_size=128 c_trace_internal_width=2 c_trace_pipeline_width=8
c_use_axi_nonsecure=0 c_use_default_acp_user_val=0 c_use_m_axi_gp0=1 c_use_m_axi_gp1=0
c_use_s_axi_acp=0 c_use_s_axi_gp0=0 c_use_s_axi_hp0=0 c_use_s_axi_hp1=0
c_use_s_axi_hp2=0 c_use_s_axi_hp3=0 core_container=NA iptotal=1
use_trace_data_edge_detector=0 x_ipcorerevision=5 x_iplanguage=VERILOG x_iplibrary=ip
x_ipname=processing_system7 x_ipproduct=Vivado 2017.2 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com
x_ipversion=5.5

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-ruledecks=default::[not_specified] -upgrade_cw=default::[not_specified] -waived=default::[not_specified]

report_methodology
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-waived=default::[not_specified]
results
timing-18=2

report_power
command_line_options
-advisory=default::[not_specified] -append=default::[not_specified] -file=[specified] -format=default::text
-hier=default::power -l=default::[not_specified] -name=default::[not_specified] -no_propagation=default::[not_specified]
-return_string=default::[not_specified] -rpx=[specified] -verbose=default::[not_specified] -vid=default::[not_specified]
-xpe=default::[not_specified]
usage
airflow=250 (LFM) ambient_temp=25.0 (C) bi-dir_toggle=12.500000 bidir_output_enable=1.000000
board_layers=8to11 (8 to 11 Layers) board_selection=medium (10"x10") clocks=0.004952 confidence_level_clock_activity=High
confidence_level_design_state=High confidence_level_device_models=High confidence_level_internal_activity=Medium confidence_level_io_activity=High
confidence_level_overall=Medium customer=TBD customer_class=TBD devstatic=0.130230
die=xc7z010clg400-1 dsp_output_toggle=12.500000 dynamic=1.569492 effective_thetaja=11.5
enable_probability=0.990000 family=zynq ff_toggle=12.500000 flow_state=routed
heatsink=none i/o=0.000136 input_toggle=12.500000 junction_temp=44.6 (C)
logic=0.004031 mgtavcc_dynamic_current=0.000000 mgtavcc_static_current=0.000000 mgtavcc_total_current=0.000000
mgtavcc_voltage=1.000000 mgtavtt_dynamic_current=0.000000 mgtavtt_static_current=0.000000 mgtavtt_total_current=0.000000
mgtavtt_voltage=1.200000 mgtvccaux_dynamic_current=0.000000 mgtvccaux_static_current=0.000000 mgtvccaux_total_current=0.000000
mgtvccaux_voltage=1.800000 netlist_net_matched=NA off-chip_power=0.000000 on-chip_power=1.699722
output_enable=1.000000 output_load=5.000000 output_toggle=12.500000 package=clg400
pct_clock_constrained=2.000000 pct_inputs_defined=0 platform=nt64 process=typical
ps7=1.556417 ram_enable=50.000000 ram_write=50.000000 read_saif=False
set/reset_probability=0.000000 signal_rate=False signals=0.003957 simulation_file=None
speedgrade=-1 static_prob=False temp_grade=commercial thetajb=9.3 (C/W)
thetasa=0.0 (C/W) toggle_rate=False user_board_temp=25.0 (C) user_effective_thetaja=11.5
user_junc_temp=44.6 (C) user_thetajb=9.3 (C/W) user_thetasa=0.0 (C/W) vccadc_dynamic_current=0.000000
vccadc_static_current=0.020000 vccadc_total_current=0.020000 vccadc_voltage=1.800000 vccaux_dynamic_current=0.000005
vccaux_io_dynamic_current=0.000000 vccaux_io_static_current=0.000000 vccaux_io_total_current=0.000000 vccaux_io_voltage=1.800000
vccaux_static_current=0.011718 vccaux_total_current=0.011723 vccaux_voltage=1.800000 vccbram_dynamic_current=0.000000
vccbram_static_current=0.000435 vccbram_total_current=0.000435 vccbram_voltage=1.000000 vccint_dynamic_current=0.012940
vccint_static_current=0.007061 vccint_total_current=0.020001 vccint_voltage=1.000000 vcco12_dynamic_current=0.000000
vcco12_static_current=0.000000 vcco12_total_current=0.000000 vcco12_voltage=1.200000 vcco135_dynamic_current=0.000000
vcco135_static_current=0.000000 vcco135_total_current=0.000000 vcco135_voltage=1.350000 vcco15_dynamic_current=0.000000
vcco15_static_current=0.000000 vcco15_total_current=0.000000 vcco15_voltage=1.500000 vcco18_dynamic_current=0.000000
vcco18_static_current=0.000000 vcco18_total_current=0.000000 vcco18_voltage=1.800000 vcco25_dynamic_current=0.000000
vcco25_static_current=0.000000 vcco25_total_current=0.000000 vcco25_voltage=2.500000 vcco33_dynamic_current=0.000038
vcco33_static_current=0.001000 vcco33_total_current=0.001038 vcco33_voltage=3.300000 vcco_ddr_dynamic_current=0.455616
vcco_ddr_static_current=0.002000 vcco_ddr_total_current=0.457616 vcco_ddr_voltage=1.500000 vcco_mio0_dynamic_current=0.001750
vcco_mio0_static_current=0.001000 vcco_mio0_total_current=0.002750 vcco_mio0_voltage=3.300000 vcco_mio1_dynamic_current=0.002965
vcco_mio1_static_current=0.001000 vcco_mio1_total_current=0.003965 vcco_mio1_voltage=1.800000 vccpaux_dynamic_current=0.074376
vccpaux_static_current=0.010330 vccpaux_total_current=0.084706 vccpaux_voltage=1.800000 vccpint_dynamic_current=0.703255
vccpint_static_current=0.030247 vccpint_total_current=0.733502 vccpint_voltage=1.000000 vccpll_dynamic_current=0.013749
vccpll_static_current=0.003000 vccpll_total_current=0.016749 vccpll_voltage=1.800000 version=2017.2

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_used=1 bufgctrl_util_percentage=3.13
bufhce_available=48 bufhce_fixed=0 bufhce_used=0 bufhce_util_percentage=0.00
bufio_available=8 bufio_fixed=0 bufio_used=0 bufio_util_percentage=0.00
bufmrce_available=4 bufmrce_fixed=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=8 bufr_fixed=0 bufr_used=0 bufr_util_percentage=0.00
mmcme2_adv_available=2 mmcme2_adv_fixed=0 mmcme2_adv_used=0 mmcme2_adv_util_percentage=0.00
plle2_adv_available=2 plle2_adv_fixed=0 plle2_adv_used=0 plle2_adv_util_percentage=0.00
dsp
dsps_available=80 dsps_fixed=0 dsps_used=0 dsps_util_percentage=0.00
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=1 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=1 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=1 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=1 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=60 block_ram_tile_fixed=0 block_ram_tile_used=0 block_ram_tile_util_percentage=0.00
ramb18_available=120 ramb18_fixed=0 ramb18_used=0 ramb18_util_percentage=0.00
ramb36_fifo_available=60 ramb36_fifo_fixed=0 ramb36_fifo_used=0 ramb36_fifo_util_percentage=0.00
primitives
bibuf_functional_category=IO bibuf_used=130 bufg_functional_category=Clock bufg_used=1
carry4_functional_category=CarryLogic carry4_used=108 fdre_functional_category=Flop & Latch fdre_used=1057
fdse_functional_category=Flop & Latch fdse_used=52 lut1_functional_category=LUT lut1_used=22
lut2_functional_category=LUT lut2_used=189 lut3_functional_category=LUT lut3_used=397
lut4_functional_category=LUT lut4_used=283 lut5_functional_category=LUT lut5_used=130
lut6_functional_category=LUT lut6_used=236 muxf7_functional_category=MuxFx muxf7_used=4
obuf_functional_category=IO obuf_used=2 ps7_functional_category=Specialized Resource ps7_used=1
srl16e_functional_category=Distributed Memory srl16e_used=19 srlc32e_functional_category=Distributed Memory srlc32e_used=47
slice_logic
f7_muxes_available=8800 f7_muxes_fixed=0 f7_muxes_used=4 f7_muxes_util_percentage=0.05
f8_muxes_available=4400 f8_muxes_fixed=0 f8_muxes_used=0 f8_muxes_util_percentage=0.00
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=0 lut_as_logic_available=17600 lut_as_logic_fixed=0
lut_as_logic_used=1016 lut_as_logic_util_percentage=5.77 lut_as_memory_available=6000 lut_as_memory_fixed=0
lut_as_memory_used=62 lut_as_memory_util_percentage=1.03 lut_as_shift_register_fixed=0 lut_as_shift_register_used=62
register_as_flip_flop_available=35200 register_as_flip_flop_fixed=0 register_as_flip_flop_used=1109 register_as_flip_flop_util_percentage=3.15
register_as_latch_available=35200 register_as_latch_fixed=0 register_as_latch_used=0 register_as_latch_util_percentage=0.00
slice_luts_available=17600 slice_luts_fixed=0 slice_luts_used=1078 slice_luts_util_percentage=6.13
slice_registers_available=35200 slice_registers_fixed=0 slice_registers_used=1109 slice_registers_util_percentage=3.15
fully_used_lut_ff_pairs_fixed=3.15 fully_used_lut_ff_pairs_used=157 lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=0
lut_as_logic_available=17600 lut_as_logic_fixed=0 lut_as_logic_used=1016 lut_as_logic_util_percentage=5.77
lut_as_memory_available=6000 lut_as_memory_fixed=0 lut_as_memory_used=62 lut_as_memory_util_percentage=1.03
lut_as_shift_register_fixed=0 lut_as_shift_register_used=62 lut_ff_pairs_with_one_unused_flip_flop_fixed=62 lut_ff_pairs_with_one_unused_flip_flop_used=449
lut_ff_pairs_with_one_unused_lut_output_fixed=449 lut_ff_pairs_with_one_unused_lut_output_used=437 lut_flip_flop_pairs_available=17600 lut_flip_flop_pairs_fixed=0
lut_flip_flop_pairs_used=629 lut_flip_flop_pairs_util_percentage=3.57 slice_available=4400 slice_fixed=0
slice_used=397 slice_util_percentage=9.02 slicel_fixed=0 slicel_used=251
slicem_fixed=0 slicem_used=146 unique_control_sets_used=63 using_o5_and_o6_fixed=63
using_o5_and_o6_used=4 using_o5_output_only_fixed=4 using_o5_output_only_used=0 using_o6_output_only_fixed=0
using_o6_output_only_used=58
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=0 bscane2_util_percentage=0.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=0 xadc_used=0 xadc_util_percentage=0.00

router
usage
actual_expansions=863446 bogomips=0 bram18=0 bram36=0
bufg=0 bufr=0 congestion_level=0 ctrls=63
dsp=0 effort=2 estimated_expansions=1321512 ff=1109
global_clocks=1 high_fanout_nets=2 iob=2 lut=1148
movable_instances=2829 nets=4187 pins=17895 pll=0
router_runtime=0.000000 router_timing_driven=1 threads=2 timing_constraints_exist=1

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -directive=default::default -fanout_limit=default::10000 -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified] -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] -max_bram=default::-1 -max_bram_cascade_height=default::-1 -max_dsp=default::-1
-max_uram=default::-1 -max_uram_cascade_height=default::-1 -mode=default::default -name=default::[not_specified]
-no_lc=default::[not_specified] -no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified] -part=xc7z010clg400-1
-resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] -seu_protect=default::none -sfcu=default::[not_specified] -shreg_min_size=default::3
-top=design_1_wrapper -verilog_define=default::[not_specified]
usage
elapsed=00:00:49s hls_ip=0 memory_gain=384.664MB memory_peak=667.758MB