--Addes three to 3 different sections of a 12 bit value used to simplify code for ConvertHexToDec
--@author Sam Malicoat, Ryan Kendall
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Add3_3times is
            Port ( Input : in STD_LOGIC_VECTOR (11 downto 0);
                   Output : out STD_LOGIC_VECTOR (11 downto 0));
end Add3_3times;

architecture Behavioral of Add3_3Times is
component Add3 Port ( input : in STD_LOGIC_VECTOR (3 downto 0);
                     output : out STD_LOGIC_VECTOR (3 downto 0));
end component;

begin

sect1: Add3 port map(
                input=>Input(11 downto 8),
                output=>Output(11 downto 8));
                
sect2: Add3 port map(
                input=>Input(7 downto 4),
                output=>Output(7 downto 4));
                
sect3: Add3 port map(
                input=>Input(3 downto 0),
                output=>Output(3 downto 0));

end Behavioral;