---------------------------------------------------------------------------------- -- Company: Cal Poly -- Engineer: Ian Nielsen and Omri Nissan -- -- Create Date: 20:09:22 11/27/2014 -- Design Name: -- Module Name: comparator_match - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.std_logic_arith.all; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity comparator_match is Port ( --en : in std_logic; clk : in std_logic; led : in STD_LOGIC_VECTOR (2 downto 0); btnm : in STD_LOGIC_VECTOR (2 downto 0); m : out STD_LOGIC; nm : out STD_LOGIC); end comparator_match; architecture Behavioral of comparator_match is begin comp : process (btnm, led, clk) begin if rising_edge(clk) then --if (en = '1') then if (btnm = "000") then nm <= '0'; m <= '0'; elsif (btnm = led) then m <= '1'; nm <= '0'; else m <= '0'; nm <= '1'; end if; -- else -- nm <= '0'; -- m <= '0'; -- end if; end if; end process comp; end Behavioral;