---------------------------------------------------------------------------------- -- Company: Ratner Engineering -- Engineer: bryan mealy -- Engineer2: Neal Nguyen & Bryan Bellin (made some changes from the original) -- Create Date: 15:27:40 12/27/2010 -- Design Name: -- Module Name: clk_div.vhd -- Project Name: -- Target Devices: -- Tool versions: -- Description: This divides the input clock frequency into a slower -- frequency. The frequency is set by the the MAX_COUNT -- constant in the declarative region of the architecture. -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -------------------------------------------------------------------------------- ----------------------------------------------------------------------- ----------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; ----------------------------------------------------------------------- -- Module to divide the clock ----------------------------------------------------------------------- entity clk_div1 is Port ( clk : in std_logic; div_factor : in STD_LOGIC_VECTOR(27 downto 0) := X"0000000"; sclk : out std_logic); end clk_div1; architecture my_clk_div of clk_div1 is --constant max_count : integer := (div_factor); signal tmp_clk : std_logic := '0'; begin my_div: process (clk,tmp_clk) variable div_cnt : std_logic_vector(27 downto 0) := X"0000000"; begin if (rising_edge(clk)) then if (div_cnt = div_factor) then--MAX_COUNT) then tmp_clk <= not tmp_clk; div_cnt := X"0000000"; else div_cnt := div_cnt + X"0000001"; end if; end if; sclk <= tmp_clk; end process my_div; end my_clk_div;