---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 10:59:38 10/06/2014 -- Design Name: -- Module Name: lab3 - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. library UNISIM; use UNISIM.VComponents.all; entity ripplecarryadder is Port ( A : in std_logic_vector(7 downto 0); B : in STD_LOGIC_VECTOR (7 downto 0); Enable : in std_logic; reset : in std_logic; Sum : out STD_LOGIC_VECTOR (7 downto 0); Carryout : out STD_LOGIC_VECTOR (0 downto 0); success : out std_logic); end Ripplecarryadder; architecture Behavioral of ripplecarryadder is component full_adder is port( A: in std_logic; B: in std_logic; enable : in std_logic; carryin : in std_logic; reset : in std_logic; Sum : out std_logic; success : out std_logic; carryout: out std_logic); end component full_adder; signal t1: std_logic; signal t2: std_logic; signal t3: std_logic; signal t4: std_logic; signal t5: std_logic; signal t6: std_logic; signal t7: std_logic; signal s1: std_logic; signal s2: std_logic; signal s3: std_logic; signal s4: std_logic; signal s5: std_logic; signal s6: std_logic; signal s7: std_logic; signal s8: std_logic; begin FA0 : full_adder port map( A => A(0), B => B(0), enable => enable, carryin =>'0', reset => reset, Sum => Sum(0), success => s1, Carryout => t1); FA1 : full_adder port map( A => A(1), B => B(1), enable => enable, carryin => t1, reset => reset, Sum => Sum(1), success => s2, Carryout => t2); FA2 : full_adder port map( A => A(2), B => B(2), enable => enable, carryin => t2, reset => reset, Sum => Sum(2), success => s3, Carryout => t3); FA3 : full_adder port map( A => A(3), B => B(3), enable => enable, carryin => t3, reset => reset, Sum => Sum(3), success => s4, Carryout => t4); FA4 : full_adder port map( A => A(4), B => B(4), enable => enable, carryin => t4, reset => reset, Sum => Sum(4), success => s5, Carryout => t5); FA5 : full_adder port map( A => A(5), B => B(5), enable => enable, carryin => t5, reset => reset, Sum => Sum(5), success => s6, Carryout => t6); FA6 : full_adder port map( A => A(6), B => B(6), enable => enable, carryin => t6, reset => reset, Sum => Sum(6), success => s7, Carryout => t7); FA7 : full_adder port map( A => A(7), B => B(7), enable => enable, carryin => t7, reset => reset, Sum => Sum(7), success => s8, Carryout => carryout(0)); process(s1,s2,s3,s4,s5,s6,s7,s8,enable) begin success <= s1 and s2 and s3 and s4 and s5 and s6 and s7 and s8; end process; end Behavioral;