---------------------------------------------------------------------------------- -- Company: Cal Poly SLO -- Engineer: Neal Nguyen & Bryan Bellin -- -- Create Date: 15:36:04 11/21/2014 -- Design Name: Shift Register -- Module Name: ShiftRegister - Behavioral -- Project Name: BitRunner -- Target Devices: Nexys 3 -- -- Description: Create a shift register for the obstacles. You’ll need a clock divider to make the shift register obstacles run at comprehendible speeds. ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity ShiftRegister is Port ( cclk : in STD_LOGIC; -- takes in a clk div_factor : in STD_LOGIC_VECTOR(27 downto 0); --a new divide factor to pass in to change the speed reset : in STD_LOGIC; --resets if this is a 1 lfsr7 : out STD_LOGIC_VECTOR (7 downto 0)); --the shift register for the obstacles end ShiftRegister; architecture Behavioral of ShiftRegister is component clk_div1 --the clk divider so that the game doesn't go as fast as the clock on the board Port ( clk : in std_logic; div_factor : in STD_LOGIC_VECTOR(27 downto 0); sclk : out std_logic); end component; signal lfsr : std_logic_vector(7 downto 0) := "00000001"; --temp signal for current shift register signal lfsr_next : std_logic_vector(7 downto 0) := "00000001"; --next signal for shift register signal new_clk : std_logic; --stores the new clock output by the clock divider begin my_clk: clk_div1 port map (clk => cclk, div_factor => div_factor, sclk => new_clk ); lfsr_seq : process (new_clk, reset, lfsr_next) begin if (reset = '1') then --if reset is 1 then reset to '1' lfsr <= "00000001"; elsif (rising_edge(new_clk)) then --else on rising edge current lfsr becomes the next state lfsr <= lfsr_next; end if; end process lfsr_seq; lfsr_comb : process(lfsr, new_clk, reset) begin lfsr_next (7 downto 1) <= lfsr (6 downto 0); -- compounded way of saying shift value down the line lfsr_next (0) <= lfsr(7) xor lfsr(1); --gives the next first bit this in order to produce some randomness end process lfsr_comb; lfsr7 <= lfsr; --the output gets the current lfsr state end Behavioral;