
# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 14.2 Build EDK_P.28xd
# Tue Jul 31 18:47:17 2012
# Target Board:  xilinx.com zc702 Rev C
# Family:    zynq
# Device:    xc7z020
# Package:   clg484
# Speed Grade:  -1
# ##############################################################################
 PARAMETER VERSION = 2.1.0


 PORT processing_system7_0_MIO = processing_system7_0_MIO, DIR = IO, VEC = [53:0]
 PORT processing_system7_0_PS_SRSTB = processing_system7_0_PS_SRSTB, DIR = I
 PORT processing_system7_0_PS_CLK = processing_system7_0_PS_CLK, DIR = I, SIGIS = CLK
 PORT processing_system7_0_PS_PORB = processing_system7_0_PS_PORB, DIR = I
 PORT processing_system7_0_DDR_Clk = processing_system7_0_DDR_Clk, DIR = IO, SIGIS = CLK
 PORT processing_system7_0_DDR_Clk_n = processing_system7_0_DDR_Clk_n, DIR = IO, SIGIS = CLK
 PORT processing_system7_0_DDR_CKE = processing_system7_0_DDR_CKE, DIR = IO
 PORT processing_system7_0_DDR_CS_n = processing_system7_0_DDR_CS_n, DIR = IO
 PORT processing_system7_0_DDR_RAS_n = processing_system7_0_DDR_RAS_n, DIR = IO
 PORT processing_system7_0_DDR_CAS_n = processing_system7_0_DDR_CAS_n, DIR = IO
 PORT processing_system7_0_DDR_WEB = processing_system7_0_DDR_WEB, DIR = O
 PORT processing_system7_0_DDR_BankAddr = processing_system7_0_DDR_BankAddr, DIR = IO, VEC = [2:0]
 PORT processing_system7_0_DDR_Addr = processing_system7_0_DDR_Addr, DIR = IO, VEC = [14:0]
 PORT processing_system7_0_DDR_ODT = processing_system7_0_DDR_ODT, DIR = IO
 PORT processing_system7_0_DDR_DRSTB = processing_system7_0_DDR_DRSTB, DIR = IO, SIGIS = RST
 PORT processing_system7_0_DDR_DQ = processing_system7_0_DDR_DQ, DIR = IO, VEC = [31:0]
 PORT processing_system7_0_DDR_DM = processing_system7_0_DDR_DM, DIR = IO, VEC = [3:0]
 PORT processing_system7_0_DDR_DQS = processing_system7_0_DDR_DQS, DIR = IO, VEC = [3:0]
 PORT processing_system7_0_DDR_DQS_n = processing_system7_0_DDR_DQS_n, DIR = IO, VEC = [3:0]
 PORT processing_system7_0_DDR_VRN = processing_system7_0_DDR_VRN, DIR = IO
 PORT processing_system7_0_DDR_VRP = processing_system7_0_DDR_VRP, DIR = IO
 PORT xillybus_bus_clk = xillybus_0_xillybus_bus_clk, DIR = O
 PORT xillybus_bus_rst_n = xillybus_0_xillybus_bus_rst_n, DIR = O
 PORT xillybus_S_AXI_AWADDR = xillybus_0_xillybus_S_AXI_AWADDR, DIR = O, VEC = [31:0]
 PORT xillybus_S_AXI_AWVALID = xillybus_0_xillybus_S_AXI_AWVALID, DIR = O
 PORT xillybus_S_AXI_WDATA = xillybus_0_xillybus_S_AXI_WDATA, DIR = O, VEC = [31:0]
 PORT xillybus_S_AXI_WSTRB = xillybus_0_xillybus_S_AXI_WSTRB, DIR = O, VEC = [3:0]
 PORT xillybus_S_AXI_WVALID = xillybus_0_xillybus_S_AXI_WVALID, DIR = O
 PORT xillybus_S_AXI_BREADY = xillybus_0_xillybus_S_AXI_BREADY, DIR = O
 PORT xillybus_S_AXI_ARADDR = xillybus_0_xillybus_S_AXI_ARADDR, DIR = O, VEC = [31:0]
 PORT xillybus_S_AXI_ARVALID = xillybus_0_xillybus_S_AXI_ARVALID, DIR = O
 PORT xillybus_S_AXI_RREADY = xillybus_0_xillybus_S_AXI_RREADY, DIR = O
 PORT xillybus_S_AXI_ARREADY = xillybus_0_xillybus_S_AXI_ARREADY, DIR = I
 PORT xillybus_S_AXI_RDATA = xillybus_0_xillybus_S_AXI_RDATA, DIR = I, VEC = [31:0]
 PORT xillybus_S_AXI_RRESP = xillybus_0_xillybus_S_AXI_RRESP, DIR = I, VEC = [1:0]
 PORT xillybus_S_AXI_RVALID = xillybus_0_xillybus_S_AXI_RVALID, DIR = I
 PORT xillybus_S_AXI_WREADY = xillybus_0_xillybus_S_AXI_WREADY, DIR = I
 PORT xillybus_S_AXI_BRESP = xillybus_0_xillybus_S_AXI_BRESP, DIR = I, VEC = [1:0]
 PORT xillybus_S_AXI_BVALID = xillybus_0_xillybus_S_AXI_BVALID, DIR = I
 PORT xillybus_S_AXI_AWREADY = xillybus_0_xillybus_S_AXI_AWREADY, DIR = I
 PORT xillybus_M_AXI_ARREADY = xillybus_0_xillybus_M_AXI_ARREADY, DIR = O
 PORT xillybus_M_AXI_ARVALID = xillybus_0_xillybus_M_AXI_ARVALID, DIR = I
 PORT xillybus_M_AXI_ARADDR = xillybus_0_xillybus_M_AXI_ARADDR, DIR = I, VEC = [31:0]
 PORT xillybus_M_AXI_ARLEN = xillybus_0_xillybus_M_AXI_ARLEN, DIR = I, VEC = [3:0]
 PORT xillybus_M_AXI_ARSIZE = xillybus_0_xillybus_M_AXI_ARSIZE, DIR = I, VEC = [2:0]
 PORT xillybus_M_AXI_ARBURST = xillybus_0_xillybus_M_AXI_ARBURST, DIR = I, VEC = [1:0]
 PORT xillybus_M_AXI_ARPROT = xillybus_0_xillybus_M_AXI_ARPROT, DIR = I, VEC = [2:0]
 PORT xillybus_M_AXI_ARCACHE = xillybus_0_xillybus_M_AXI_ARCACHE, DIR = I, VEC = [3:0]
 PORT xillybus_M_AXI_RREADY = xillybus_0_xillybus_M_AXI_RREADY, DIR = I
 PORT xillybus_M_AXI_RVALID = xillybus_0_xillybus_M_AXI_RVALID, DIR = O
 PORT xillybus_M_AXI_RDATA = xillybus_0_xillybus_M_AXI_RDATA, DIR = O, VEC = [63:0]
 PORT xillybus_M_AXI_RRESP = xillybus_0_xillybus_M_AXI_RRESP, DIR = O, VEC = [1:0]
 PORT xillybus_M_AXI_RLAST = xillybus_0_xillybus_M_AXI_RLAST, DIR = O
 PORT xillybus_M_AXI_AWREADY = xillybus_0_xillybus_M_AXI_AWREADY, DIR = O
 PORT xillybus_M_AXI_AWVALID = xillybus_0_xillybus_M_AXI_AWVALID, DIR = I
 PORT xillybus_M_AXI_AWADDR = xillybus_0_xillybus_M_AXI_AWADDR, DIR = I, VEC = [31:0]
 PORT xillybus_M_AXI_AWLEN = xillybus_0_xillybus_M_AXI_AWLEN, DIR = I, VEC = [3:0]
 PORT xillybus_M_AXI_AWSIZE = xillybus_0_xillybus_M_AXI_AWSIZE, DIR = I, VEC = [2:0]
 PORT xillybus_M_AXI_AWBURST = xillybus_0_xillybus_M_AXI_AWBURST, DIR = I, VEC = [1:0]
 PORT xillybus_M_AXI_AWPROT = xillybus_0_xillybus_M_AXI_AWPROT, DIR = I, VEC = [2:0]
 PORT xillybus_M_AXI_AWCACHE = xillybus_0_xillybus_M_AXI_AWCACHE, DIR = I, VEC = [3:0]
 PORT xillybus_M_AXI_WREADY = xillybus_0_xillybus_M_AXI_WREADY, DIR = O
 PORT xillybus_M_AXI_WVALID = xillybus_0_xillybus_M_AXI_WVALID, DIR = I
 PORT xillybus_M_AXI_WDATA = xillybus_0_xillybus_M_AXI_WDATA, DIR = I, VEC = [63:0]
 PORT xillybus_M_AXI_WSTRB = xillybus_0_xillybus_M_AXI_WSTRB, DIR = I, VEC = [7:0]
 PORT xillybus_M_AXI_WLAST = xillybus_0_xillybus_M_AXI_WLAST, DIR = I
 PORT xillybus_M_AXI_BREADY = xillybus_0_xillybus_M_AXI_BREADY, DIR = I
 PORT xillybus_M_AXI_BVALID = xillybus_0_xillybus_M_AXI_BVALID, DIR = O
 PORT xillybus_M_AXI_BRESP = xillybus_0_xillybus_M_AXI_BRESP, DIR = O, VEC = [1:0]
 PORT xillybus_host_interrupt = xillybus_0_xillybus_host_interrupt, DIR = I
 PORT xillyvga_0_clk_in = net_xillyvga_0_clk_in, DIR = I
 PORT xillyvga_0_vga_hsync = xillyvga_0_vga_hsync, DIR = O
 PORT xillyvga_0_vga_vsync = xillyvga_0_vga_vsync, DIR = O
 PORT xillyvga_0_vga_de = xillyvga_0_vga_de, DIR = O
 PORT xillyvga_0_vga_red = xillyvga_0_vga_red, DIR = O, VEC = [7:0]
 PORT xillyvga_0_vga_green = xillyvga_0_vga_green, DIR = O, VEC = [7:0]
 PORT xillyvga_0_vga_blue = xillyvga_0_vga_blue, DIR = O, VEC = [7:0]
 PORT xillyvga_0_vga_clk = xillyvga_0_vga_clk, DIR = O
 PORT processing_system7_0_GPIO = processing_system7_0_GPIO, DIR = IO, VEC = [55:0]
 PORT processing_system7_0_USB0_VBUS_PWRFAULT = net_processing_system7_0_USB0_VBUS_PWRFAULT, DIR = I
 PORT xillybus_lite_0_user_clk_pin = xillybus_lite_0_user_clk, DIR = O
 PORT xillybus_lite_0_user_wren_pin = xillybus_lite_0_user_wren, DIR = O
 PORT xillybus_lite_0_user_wstrb_pin = xillybus_lite_0_user_wstrb, DIR = O, VEC = [3:0]
 PORT xillybus_lite_0_user_rden_pin = xillybus_lite_0_user_rden, DIR = O
 PORT xillybus_lite_0_user_rd_data_pin = net_xillybus_lite_0_user_rd_data_pin, DIR = I, VEC = [31:0]
 PORT xillybus_lite_0_user_wr_data_pin = xillybus_lite_0_user_wr_data, DIR = O, VEC = [31:0]
 PORT xillybus_lite_0_user_addr_pin = xillybus_lite_0_user_addr, DIR = O, VEC = [31:0]
 PORT xillybus_lite_0_user_irq_pin = net_xillybus_lite_0_user_irq_pin, DIR = I


BEGIN axi_interconnect
 PARAMETER INSTANCE = axi4lite_0
 PARAMETER HW_VER = 1.06.a
 PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 0
 PORT interconnect_aclk = processing_system7_0_FCLK_CLK1
 PORT INTERCONNECT_ARESETN = processing_system7_0_M_AXI_GP0_ARESETN
END

BEGIN processing_system7
 PARAMETER INSTANCE = processing_system7_0
 PARAMETER HW_VER = 4.01.a
 PARAMETER C_DDR_RAM_HIGHADDR = 0x1FFFFFFF
 PARAMETER C_S_AXI_HP2_HIGHADDR = 0x1FFFFFFF
 PARAMETER C_USE_M_AXI_GP0 = 1
 PARAMETER C_EN_EMIO_CAN0 = 0
 PARAMETER C_EN_EMIO_CAN1 = 0
 PARAMETER C_EN_EMIO_ENET0 = 0
 PARAMETER C_EN_EMIO_ENET1 = 0
 PARAMETER C_EN_EMIO_I2C0 = 0
 PARAMETER C_EN_EMIO_I2C1 = 0
 PARAMETER C_EN_EMIO_PJTAG = 0
 PARAMETER C_EN_EMIO_SDIO0 = 0
 PARAMETER C_EN_EMIO_CD_SDIO0 = 0
 PARAMETER C_EN_EMIO_WP_SDIO0 = 0
 PARAMETER C_EN_EMIO_SDIO1 = 0
 PARAMETER C_EN_EMIO_CD_SDIO1 = 0
 PARAMETER C_EN_EMIO_WP_SDIO1 = 0
 PARAMETER C_EN_EMIO_SPI0 = 0
 PARAMETER C_EN_EMIO_SPI1 = 0
 PARAMETER C_EN_EMIO_SRAM_INT = 0
 PARAMETER C_EN_EMIO_TRACE = 0
 PARAMETER C_EN_EMIO_TTC0 = 1
 PARAMETER C_EN_EMIO_TTC1 = 0
 PARAMETER C_EN_EMIO_UART0 = 0
 PARAMETER C_EN_EMIO_UART1 = 0
 PARAMETER C_EN_EMIO_MODEM_UART0 = 0
 PARAMETER C_EN_EMIO_MODEM_UART1 = 0
 PARAMETER C_EN_EMIO_WDT = 0
 PARAMETER C_EN_QSPI = 1
 PARAMETER C_EN_SMC = 0
 PARAMETER C_EN_CAN0 = 0
 PARAMETER C_EN_CAN1 = 0
 PARAMETER C_EN_ENET0 = 1
 PARAMETER C_EN_ENET1 = 0
 PARAMETER C_EN_I2C0 = 0
 PARAMETER C_EN_I2C1 = 0
 PARAMETER C_EN_PJTAG = 0
 PARAMETER C_EN_SDIO0 = 1
 PARAMETER C_EN_SDIO1 = 0
 PARAMETER C_EN_SPI0 = 0
 PARAMETER C_EN_SPI1 = 0
 PARAMETER C_EN_TRACE = 0
 PARAMETER C_EN_TTC0 = 1
 PARAMETER C_EN_TTC1 = 0
 PARAMETER C_EN_UART0 = 0
 PARAMETER C_EN_UART1 = 1
 PARAMETER C_EN_MODEM_UART0 = 0
 PARAMETER C_EN_MODEM_UART1 = 0
 PARAMETER C_EN_USB0 = 1
 PARAMETER C_EN_USB1 = 0
 PARAMETER C_EN_WDT = 0
 PARAMETER C_EN_DDR = 1
 PARAMETER C_EN_GPIO = 1
 PARAMETER C_FCLK_CLK0_FREQ = 100000000
 PARAMETER C_FCLK_CLK1_FREQ = 100000000
 PARAMETER C_FCLK_CLK2_FREQ = 50000000
 PARAMETER C_FCLK_CLK3_FREQ = 50000000
 PARAMETER C_USE_S_AXI_GP0 = 0
 PARAMETER C_INTERCONNECT_S_AXI_GP0_MASTERS = xillybus_0.M_AXI
 PARAMETER C_USE_S_AXI_HP0 = 0
 PARAMETER C_USE_S_AXI_HP2 = 1
 PARAMETER C_INTERCONNECT_S_AXI_HP2_MASTERS = xillyvga_0.M_AXI
 PARAMETER C_S_AXI_HP2_DATA_WIDTH = 32
 PARAMETER C_EN_EMIO_GPIO = 1
 PARAMETER C_EMIO_GPIO_WIDTH = 56
 PARAMETER C_USE_CR_FABRIC = 1
 PARAMETER C_USE_S_AXI_ACP = 1
 PARAMETER C_INTERCONNECT_S_AXI_ACP_MASTERS = xillybus_0.M_AXI
 PARAMETER C_S_AXI_ACP_HIGHADDR = 0x1FFFFFFF
 BUS_INTERFACE M_AXI_GP0 = axi4lite_0
 BUS_INTERFACE S_AXI_HP2 = axi_interconnect_1
 BUS_INTERFACE S_AXI_ACP = axi_interconnect_0
 PORT MIO = processing_system7_0_MIO
 PORT PS_SRSTB = processing_system7_0_PS_SRSTB
 PORT PS_CLK = processing_system7_0_PS_CLK
 PORT PS_PORB = processing_system7_0_PS_PORB
 PORT DDR_Clk = processing_system7_0_DDR_Clk
 PORT DDR_Clk_n = processing_system7_0_DDR_Clk_n
 PORT DDR_CKE = processing_system7_0_DDR_CKE
 PORT DDR_CS_n = processing_system7_0_DDR_CS_n
 PORT DDR_RAS_n = processing_system7_0_DDR_RAS_n
 PORT DDR_CAS_n = processing_system7_0_DDR_CAS_n
 PORT DDR_WEB = processing_system7_0_DDR_WEB
 PORT DDR_BankAddr = processing_system7_0_DDR_BankAddr
 PORT DDR_Addr = processing_system7_0_DDR_Addr
 PORT DDR_ODT = processing_system7_0_DDR_ODT
 PORT DDR_DRSTB = processing_system7_0_DDR_DRSTB
 PORT DDR_DQ = processing_system7_0_DDR_DQ
 PORT DDR_DM = processing_system7_0_DDR_DM
 PORT DDR_DQS = processing_system7_0_DDR_DQS
 PORT DDR_DQS_n = processing_system7_0_DDR_DQS_n
 PORT DDR_VRN = processing_system7_0_DDR_VRN
 PORT DDR_VRP = processing_system7_0_DDR_VRP
 PORT M_AXI_GP0_ARESETN = processing_system7_0_M_AXI_GP0_ARESETN
 PORT FCLK_CLK1 = processing_system7_0_FCLK_CLK1
 PORT M_AXI_GP0_ACLK = processing_system7_0_FCLK_CLK1
 PORT IRQ_F2P = xillybus_0_Interrupt & xillybus_lite_0_host_interrupt
 PORT S_AXI_HP2_ARESETN = processing_system7_0_S_AXI_HP2_ARESETN
 PORT S_AXI_HP2_ACLK = processing_system7_0_FCLK_CLK1
 PORT GPIO = processing_system7_0_GPIO
 PORT USB0_VBUS_PWRFAULT = net_processing_system7_0_USB0_VBUS_PWRFAULT
 PORT FCLK_RESET0_N = processing_system7_0_FCLK_RESET0_N
 PORT S_AXI_ACP_ARESETN = processing_system7_0_S_AXI_ACP_ARESETN
 PORT S_AXI_ACP_ACLK = processing_system7_0_FCLK_CLK1
 PORT S_AXI_ACP_AWCACHE = 0b1111
 PORT S_AXI_ACP_AWUSER = 0b11111
 PORT S_AXI_ACP_ARCACHE = 0b1111
 PORT S_AXI_ACP_ARUSER = 0b11111
END

BEGIN xillybus
 PARAMETER INSTANCE = xillybus_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_BASEADDR = 0x50000000
 PARAMETER C_HIGHADDR = 0x50000FFF
 BUS_INTERFACE S_AXI = axi4lite_0
 BUS_INTERFACE M_AXI = axi_interconnect_0
 PORT m_axi_aclk = processing_system7_0_FCLK_CLK1
 PORT S_AXI_ACLK = processing_system7_0_FCLK_CLK1
 PORT xillybus_bus_clk = xillybus_0_xillybus_bus_clk
 PORT xillybus_bus_rst_n = xillybus_0_xillybus_bus_rst_n
 PORT xillybus_S_AXI_AWADDR = xillybus_0_xillybus_S_AXI_AWADDR
 PORT xillybus_S_AXI_AWVALID = xillybus_0_xillybus_S_AXI_AWVALID
 PORT xillybus_S_AXI_WDATA = xillybus_0_xillybus_S_AXI_WDATA
 PORT xillybus_S_AXI_WSTRB = xillybus_0_xillybus_S_AXI_WSTRB
 PORT xillybus_S_AXI_WVALID = xillybus_0_xillybus_S_AXI_WVALID
 PORT xillybus_S_AXI_BREADY = xillybus_0_xillybus_S_AXI_BREADY
 PORT xillybus_S_AXI_ARADDR = xillybus_0_xillybus_S_AXI_ARADDR
 PORT xillybus_S_AXI_ARVALID = xillybus_0_xillybus_S_AXI_ARVALID
 PORT xillybus_S_AXI_RREADY = xillybus_0_xillybus_S_AXI_RREADY
 PORT xillybus_S_AXI_ARREADY = xillybus_0_xillybus_S_AXI_ARREADY
 PORT xillybus_S_AXI_RDATA = xillybus_0_xillybus_S_AXI_RDATA
 PORT xillybus_S_AXI_RRESP = xillybus_0_xillybus_S_AXI_RRESP
 PORT xillybus_S_AXI_RVALID = xillybus_0_xillybus_S_AXI_RVALID
 PORT xillybus_S_AXI_WREADY = xillybus_0_xillybus_S_AXI_WREADY
 PORT xillybus_S_AXI_BRESP = xillybus_0_xillybus_S_AXI_BRESP
 PORT xillybus_S_AXI_BVALID = xillybus_0_xillybus_S_AXI_BVALID
 PORT xillybus_S_AXI_AWREADY = xillybus_0_xillybus_S_AXI_AWREADY
 PORT xillybus_M_AXI_ARREADY = xillybus_0_xillybus_M_AXI_ARREADY
 PORT xillybus_M_AXI_ARVALID = xillybus_0_xillybus_M_AXI_ARVALID
 PORT xillybus_M_AXI_ARADDR = xillybus_0_xillybus_M_AXI_ARADDR
 PORT xillybus_M_AXI_ARLEN = xillybus_0_xillybus_M_AXI_ARLEN
 PORT xillybus_M_AXI_ARSIZE = xillybus_0_xillybus_M_AXI_ARSIZE
 PORT xillybus_M_AXI_ARBURST = xillybus_0_xillybus_M_AXI_ARBURST
 PORT xillybus_M_AXI_ARPROT = xillybus_0_xillybus_M_AXI_ARPROT
 PORT xillybus_M_AXI_ARCACHE = xillybus_0_xillybus_M_AXI_ARCACHE
 PORT xillybus_M_AXI_RREADY = xillybus_0_xillybus_M_AXI_RREADY
 PORT xillybus_M_AXI_RVALID = xillybus_0_xillybus_M_AXI_RVALID
 PORT xillybus_M_AXI_RDATA = xillybus_0_xillybus_M_AXI_RDATA
 PORT xillybus_M_AXI_RRESP = xillybus_0_xillybus_M_AXI_RRESP
 PORT xillybus_M_AXI_RLAST = xillybus_0_xillybus_M_AXI_RLAST
 PORT xillybus_M_AXI_AWREADY = xillybus_0_xillybus_M_AXI_AWREADY
 PORT xillybus_M_AXI_AWVALID = xillybus_0_xillybus_M_AXI_AWVALID
 PORT xillybus_M_AXI_AWADDR = xillybus_0_xillybus_M_AXI_AWADDR
 PORT xillybus_M_AXI_AWLEN = xillybus_0_xillybus_M_AXI_AWLEN
 PORT xillybus_M_AXI_AWSIZE = xillybus_0_xillybus_M_AXI_AWSIZE
 PORT xillybus_M_AXI_AWBURST = xillybus_0_xillybus_M_AXI_AWBURST
 PORT xillybus_M_AXI_AWPROT = xillybus_0_xillybus_M_AXI_AWPROT
 PORT xillybus_M_AXI_AWCACHE = xillybus_0_xillybus_M_AXI_AWCACHE
 PORT xillybus_M_AXI_WREADY = xillybus_0_xillybus_M_AXI_WREADY
 PORT xillybus_M_AXI_WVALID = xillybus_0_xillybus_M_AXI_WVALID
 PORT xillybus_M_AXI_WDATA = xillybus_0_xillybus_M_AXI_WDATA
 PORT xillybus_M_AXI_WSTRB = xillybus_0_xillybus_M_AXI_WSTRB
 PORT xillybus_M_AXI_WLAST = xillybus_0_xillybus_M_AXI_WLAST
 PORT xillybus_M_AXI_BREADY = xillybus_0_xillybus_M_AXI_BREADY
 PORT xillybus_M_AXI_BVALID = xillybus_0_xillybus_M_AXI_BVALID
 PORT xillybus_M_AXI_BRESP = xillybus_0_xillybus_M_AXI_BRESP
 PORT xillybus_host_interrupt = xillybus_0_xillybus_host_interrupt
 PORT Interrupt = xillybus_0_Interrupt
END

BEGIN xillyvga
 PARAMETER INSTANCE = xillyvga_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_BASEADDR = 0x50001000
 PARAMETER C_HIGHADDR = 0x50001FFF
 BUS_INTERFACE M_AXI = axi_interconnect_1
 BUS_INTERFACE S_AXI = axi4lite_0
 PORT clk_in = net_xillyvga_0_clk_in
 PORT vga_hsync = xillyvga_0_vga_hsync
 PORT vga_vsync = xillyvga_0_vga_vsync
 PORT vga_de = xillyvga_0_vga_de
 PORT vga_red = xillyvga_0_vga_red
 PORT vga_green = xillyvga_0_vga_green
 PORT vga_blue = xillyvga_0_vga_blue
 PORT m_axi_aclk = processing_system7_0_FCLK_CLK1
 PORT S_AXI_ACLK = processing_system7_0_FCLK_CLK1
 PORT vga_clk = xillyvga_0_vga_clk
END

BEGIN axi_interconnect
 PARAMETER INSTANCE = axi_interconnect_1
 PARAMETER HW_VER = 1.06.a
 PORT INTERCONNECT_ACLK = processing_system7_0_FCLK_CLK1
 PORT INTERCONNECT_ARESETN = processing_system7_0_S_AXI_HP2_ARESETN
END

BEGIN xillybus_lite
 PARAMETER INSTANCE = xillybus_lite_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_BASEADDR = 0x50002000
 PARAMETER C_HIGHADDR = 0x50002FFF
 BUS_INTERFACE S_AXI = axi4lite_0
 PORT S_AXI_ACLK = processing_system7_0_FCLK_CLK1
 PORT host_interrupt = xillybus_lite_0_host_interrupt
 PORT user_clk = xillybus_lite_0_user_clk
 PORT user_wren = xillybus_lite_0_user_wren
 PORT user_wstrb = xillybus_lite_0_user_wstrb
 PORT user_rden = xillybus_lite_0_user_rden
 PORT user_rd_data = net_xillybus_lite_0_user_rd_data_pin
 PORT user_wr_data = xillybus_lite_0_user_wr_data
 PORT user_addr = xillybus_lite_0_user_addr
 PORT user_irq = net_xillybus_lite_0_user_irq_pin
END

BEGIN axi_interconnect
 PARAMETER INSTANCE = axi_interconnect_0
 PARAMETER HW_VER = 1.06.a
 PORT INTERCONNECT_ACLK = processing_system7_0_FCLK_CLK1
 PORT INTERCONNECT_ARESETN = processing_system7_0_S_AXI_ACP_ARESETN
END

