library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clk_div_reset is
generic (
    INFREQ                : integer := 50000000; --frequentie in Hz (frequentie FPGA is 50 MHz)
    OUTFREQ               : integer := 17000
);  
Port (
    clk             :IN     STD_LOGIC;
    reset           :IN     STD_LOGIC;
    reset_seen      :OUT    STD_LOGIC;
    clkOut          :OUT    STD_LOGIC
);
end clk_div_reset;
architecture Behavioral of clk_div_reset is
begin
    deler : process(clk)
        variable counter : integer := 0;
        variable clk_int : std_logic := '0';
    begin
        if rising_edge(clk) then
            counter := counter + 1;
            reset_seen <= '0';
            if reset = '1' then
                reset_seen <= '1';
                counter := 0;
                clk_int := '0';
            -- 2*requested frequency: only counting periods (rising edges), not edges (both rising and falling edges),
            -- one period has two edges, so to compensate, the input frequency is devided by two
            -- to see this, take INFREQ = OUTFREQ. If INFREQ/OUTFREQ = 1, the output would change every rising edge,
            -- giving a period of 2* the period of the input clock. or a frequency that is half of the original frequency, and not the same
            elsif counter = INFREQ/(2*OUTFREQ) then
                counter := 0;
                clk_int := not clk_int;
            end if;
        end if;
        clkOut <= clk_int;
    end process;
end Behavioral;