BEGIN xillybus_lite

## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION HDL = VERILOG
OPTION STYLE = BLACKBOX
OPTION IP_GROUP = MICROBLAZE:USER
OPTION DESC = XILLYBUS_LITE
OPTION LONG_DESC = Xillybus Lite plain register interface
OPTION ARCH_SUPPORT_MAP = (spartan6t=PRODUCTION, spartan6=PRODUCTION, spartan6l=PRODUCTION, qspartan6t=PRODUCTION, qspartan6=PRODUCTION, aspartan6t=PRODUCTION, aspartan6=PRODUCTION, virtex6lx=PRODUCTION, virtex6sx=PRODUCTION, virtex6cx=PRODUCTION, virtex6llx=PRODUCTION, virtex6lsx=PRODUCTION, qspartan6l=PRODUCTION, qvirtex6lx=PRODUCTION, qvirtex6sx=PRODUCTION, qvirtex6fx=PRODUCTION, qvirtex6tx=PRODUCTION, virtex7=PRODUCTION, kintex7=PRODUCTION, artix7=PRODUCTION, zynq=PRODUCTION, virtex7l=PRODUCTION, kintex7l=PRODUCTION, aartix7=PRODUCTION, artix7l=PRODUCTION, virtex7ht=PRODUCTION, qvirtex7=PRODUCTION, qkintex7=PRODUCTION, qkintex7l=PRODUCTION, qartix7=PRODUCTION, qartix7l=PRODUCTION, azynq=PRODUCTION, qzynq=PRODUCTION, qvirtex7l=PRODUCTION)

## Bus Interfaces
BUS_INTERFACE BUS = S_AXI, BUS_STD = AXI, BUS_TYPE = SLAVE

## Generics for VHDL or Parameters for Verilog
PARAMETER C_S_AXI_DATA_WIDTH = 32, DT = INTEGER, BUS = S_AXI, ASSIGNMENT = CONSTANT, TYPE = NON_HDL
PARAMETER C_S_AXI_ADDR_WIDTH = 32, DT = INTEGER, BUS = S_AXI, ASSIGNMENT = CONSTANT, TYPE = NON_HDL
PARAMETER C_S_AXI_MIN_SIZE = 0x000001ff, DT = std_logic_vector, BUS = S_AXI, TYPE = NON_HDL
PARAMETER C_USE_WSTRB = 1, DT = INTEGER, ASSIGNMENT = CONSTANT, TYPE = NON_HDL
PARAMETER C_DPHASE_TIMEOUT = 8, DT = INTEGER, TYPE = NON_HDL
PARAMETER C_BASEADDR = 0xffffffff, DT = std_logic_vector, MIN_SIZE = 0x100, PAIR = C_HIGHADDR, ADDRESS = BASE, BUS = S_AXI, TYPE = NON_HDL
PARAMETER C_HIGHADDR = 0x00000000, DT = std_logic_vector, PAIR = C_BASEADDR, ADDRESS = HIGH, BUS = S_AXI, TYPE = NON_HDL
PARAMETER C_SLV_AWIDTH = 32, DT = INTEGER, TYPE = NON_HDL
PARAMETER C_SLV_DWIDTH = 32, DT = INTEGER, TYPE = NON_HDL
PARAMETER C_MAX_BURST_LEN = 16, DT = INTEGER, ASSIGNMENT = CONSTANT, TYPE = NON_HDL
PARAMETER C_NATIVE_DATA_WIDTH = 32, DT = INTEGER, ASSIGNMENT = CONSTANT, TYPE = NON_HDL
PARAMETER C_S_AXI_PROTOCOL = AXI4LITE, TYPE = NON_HDL, ASSIGNMENT = CONSTANT, DT = STRING, BUS = S_AXI

## Ports
PORT S_AXI_ACLK = "", DIR = I, SIGIS = CLK, BUS = S_AXI
PORT S_AXI_ARESETN = ARESETN, DIR = I, SIGIS = RST, BUS = S_AXI
PORT S_AXI_AWADDR = AWADDR, DIR = I, VEC = [31:0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_AWVALID = AWVALID, DIR = I, BUS = S_AXI
PORT S_AXI_WDATA = WDATA, DIR = I, VEC = [31:0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_WSTRB = WSTRB, DIR = I, VEC = [3:0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_WVALID = WVALID, DIR = I, BUS = S_AXI
PORT S_AXI_BREADY = BREADY, DIR = I, BUS = S_AXI
PORT S_AXI_ARADDR = ARADDR, DIR = I, VEC = [31:0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_ARVALID = ARVALID, DIR = I, BUS = S_AXI
PORT S_AXI_RREADY = RREADY, DIR = I, BUS = S_AXI
PORT S_AXI_ARREADY = ARREADY, DIR = O, BUS = S_AXI
PORT S_AXI_RDATA = RDATA, DIR = O, VEC = [31:0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_RRESP = RRESP, DIR = O, VEC = [1:0], BUS = S_AXI
PORT S_AXI_RVALID = RVALID, DIR = O, BUS = S_AXI
PORT S_AXI_WREADY = WREADY, DIR = O, BUS = S_AXI
PORT S_AXI_BRESP = BRESP, DIR = O, VEC = [1:0], BUS = S_AXI
PORT S_AXI_BVALID = BVALID, DIR = O, BUS = S_AXI
PORT S_AXI_AWREADY = AWREADY, DIR = O, BUS = S_AXI

PORT host_interrupt = "", DIR = O, INTERRUPT_PRIORITY = LOW, SIGIS = INTERRUPT, SENSITIVITY = EDGE_RISING

PORT user_clk = "", DIR = O
PORT user_wren = "", DIR = O
PORT user_wstrb = "", DIR = O, VEC = [3:0]
PORT user_rden = "", DIR = O
PORT user_rd_data = "", DIR = I, VEC = [31:0]
PORT user_wr_data = "", DIR = O, VEC = [31:0]
PORT user_addr = "", DIR = O, VEC = [31:0]

PORT user_irq = "", DIR = I

END
