Device Usage Page (usage_statistics_webtalk.html)

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software_version_and_target_device
betaFALSE build_version1756540
date_generatedMon Apr 10 21:06:35 2017 os_platformWIN64
product_versionVivado v2016.4 (64-bit) project_id573a607a9e594642b15c3257d6766430
project_iteration4 random_idee5410164abf5da690afbc2b8587a625
registration_id211039246_1777507825_210603171_363 route_designTRUE
target_devicexc7a200t target_familyartix7
target_packagesbg484 target_speed-1
tool_flowVivado

user_environment
cpu_nameIntel(R) Core(TM) i7-4700HQ CPU @ 2.40GHz cpu_speed2394 MHz
os_nameMicrosoft Windows 8 or later , 64-bit os_releasemajor release (build 9200)
system_ram17.000 GB total_processors1

vivado_usage
java_command_handlers
addsources=1 autoconnecttarget=1 closeproject=1 fliptoviewtaskrtlanalysis=3
launchprogramfpga=4 managecompositetargets=6 openhardwaremanager=5 openrecenttarget=1
programdevice=4 recustomizecore=1 runbitgen=4 runimplementation=1
runschematic=1 viewtaskprojectmanager=6
other_data
guimode=3
project_data
constraintsetcount=1 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=4 export_simulation_ies=4
export_simulation_modelsim=4 export_simulation_questa=4 export_simulation_riviera=4 export_simulation_vcs=4
export_simulation_xsim=4 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=0 simulator_language=VHDL srcsetcount=12 synthesisstrategy=Vivado Synthesis Defaults
target_language=VHDL target_simulator=XSim totalimplruns=4 totalsynthesisruns=4

unisim_transformation
post_unisim_transformation
bufg=7 carry4=36 fdce=51 fdpe=5
fdre=455 fdse=3 fifo18e1=1 gnd=28
ibuf=6 ibufds=4 iserdese2=6 lut1=117
lut2=78 lut3=89 lut4=71 lut5=78
lut6=268 mmcme2_adv=2 muxf7=36 muxf8=2
obuf=11 obufds=4 obuft=1 oserdese2=6
srl16e=2 vcc=24
pre_unisim_transformation
bufg=7 carry4=36 fdce=51 fdpe=5
fdre=455 fdse=3 fifo18e1=1 gnd=28
ibuf=7 ibufds=4 iobuf=1 iserdese2=6
lut1=117 lut2=78 lut3=89 lut4=71
lut5=78 lut6=268 mmcme2_adv=2 muxf7=36
muxf8=2 obuf=11 obufds=4 oserdese2=6
srl16e=2 vcc=24

ip_statistics
clk_wiz_v5_3_3_0/1
clkin1_period=6.734 clkin2_period=10.0 clock_mgr_type=NA component_name=dv_seri_clk
core_container=NA enable_axi=0 feedback_source=FDBK_AUTO feedback_type=SINGLE
iptotal=1 manual_override=false num_out_clk=2 primitive=MMCM
use_dyn_phase_shift=false use_dyn_reconfig=false use_inclk_stopped=false use_inclk_switchover=false
use_locked=true use_max_i_jitter=false use_min_o_jitter=true use_phase_alignment=true
use_power_down=false use_reset=true
clk_wiz_v5_3_3_0/2
clkin1_period=6.734 clkin2_period=10.0 clock_mgr_type=NA component_name=dvi_deser_clk
core_container=NA enable_axi=0 feedback_source=FDBK_AUTO feedback_type=SINGLE
iptotal=1 manual_override=false num_out_clk=2 primitive=MMCM
use_dyn_phase_shift=false use_dyn_reconfig=false use_inclk_stopped=false use_inclk_switchover=false
use_locked=true use_max_i_jitter=false use_min_o_jitter=false use_phase_alignment=true
use_power_down=false use_reset=true
fifo_generator_v13_1_3/1
c_add_ngc_constraint=0 c_application_type_axis=0 c_application_type_rach=0 c_application_type_rdch=0
c_application_type_wach=0 c_application_type_wdch=0 c_application_type_wrch=0 c_axi_addr_width=32
c_axi_aruser_width=1 c_axi_awuser_width=1 c_axi_buser_width=1 c_axi_data_width=64
c_axi_id_width=1 c_axi_len_width=8 c_axi_lock_width=1 c_axi_ruser_width=1
c_axi_type=1 c_axi_wuser_width=1 c_axis_tdata_width=8 c_axis_tdest_width=1
c_axis_tid_width=1 c_axis_tkeep_width=1 c_axis_tstrb_width=1 c_axis_tuser_width=4
c_axis_type=0 c_common_clock=0 c_count_type=0 c_data_count_width=9
c_default_value=BlankString c_din_width=27 c_din_width_axis=1 c_din_width_rach=32
c_din_width_rdch=64 c_din_width_wach=1 c_din_width_wdch=64 c_din_width_wrch=2
c_dout_rst_val=0 c_dout_width=27 c_en_safety_ckt=0 c_enable_rlocs=0
c_enable_rst_sync=1 c_error_injection_type=0 c_error_injection_type_axis=0 c_error_injection_type_rach=0
c_error_injection_type_rdch=0 c_error_injection_type_wach=0 c_error_injection_type_wdch=0 c_error_injection_type_wrch=0
c_family=artix7 c_full_flags_rst_val=0 c_has_almost_empty=0 c_has_almost_full=0
c_has_axi_aruser=0 c_has_axi_awuser=0 c_has_axi_buser=0 c_has_axi_id=0
c_has_axi_rd_channel=1 c_has_axi_ruser=0 c_has_axi_wr_channel=1 c_has_axi_wuser=0
c_has_axis_tdata=1 c_has_axis_tdest=0 c_has_axis_tid=0 c_has_axis_tkeep=0
c_has_axis_tlast=0 c_has_axis_tready=1 c_has_axis_tstrb=0 c_has_axis_tuser=1
c_has_backup=0 c_has_data_count=0 c_has_data_counts_axis=0 c_has_data_counts_rach=0
c_has_data_counts_rdch=0 c_has_data_counts_wach=0 c_has_data_counts_wdch=0 c_has_data_counts_wrch=0
c_has_int_clk=0 c_has_master_ce=0 c_has_meminit_file=0 c_has_overflow=0
c_has_prog_flags_axis=0 c_has_prog_flags_rach=0 c_has_prog_flags_rdch=0 c_has_prog_flags_wach=0
c_has_prog_flags_wdch=0 c_has_prog_flags_wrch=0 c_has_rd_data_count=0 c_has_rd_rst=0
c_has_rst=1 c_has_slave_ce=0 c_has_srst=0 c_has_underflow=0
c_has_valid=0 c_has_wr_ack=0 c_has_wr_data_count=0 c_has_wr_rst=0
c_implementation_type=6 c_implementation_type_axis=1 c_implementation_type_rach=1 c_implementation_type_rdch=1
c_implementation_type_wach=1 c_implementation_type_wdch=1 c_implementation_type_wrch=1 c_init_wr_pntr_val=0
c_interface_type=0 c_memory_type=4 c_mif_file_name=BlankString c_msgon_val=1
c_optimization_mode=0 c_overflow_low=0 c_power_saving_mode=0 c_preload_latency=1
c_preload_regs=0 c_prim_fifo_type=512x36 c_prim_fifo_type_axis=1kx18 c_prim_fifo_type_rach=512x36
c_prim_fifo_type_rdch=1kx36 c_prim_fifo_type_wach=512x36 c_prim_fifo_type_wdch=1kx36 c_prim_fifo_type_wrch=512x36
c_prog_empty_thresh_assert_val=5 c_prog_empty_thresh_assert_val_axis=1022 c_prog_empty_thresh_assert_val_rach=1022 c_prog_empty_thresh_assert_val_rdch=1022
c_prog_empty_thresh_assert_val_wach=1022 c_prog_empty_thresh_assert_val_wdch=1022 c_prog_empty_thresh_assert_val_wrch=1022 c_prog_empty_thresh_negate_val=6
c_prog_empty_type=0 c_prog_empty_type_axis=0 c_prog_empty_type_rach=0 c_prog_empty_type_rdch=0
c_prog_empty_type_wach=0 c_prog_empty_type_wdch=0 c_prog_empty_type_wrch=0 c_prog_full_thresh_assert_val=505
c_prog_full_thresh_assert_val_axis=1023 c_prog_full_thresh_assert_val_rach=1023 c_prog_full_thresh_assert_val_rdch=1023 c_prog_full_thresh_assert_val_wach=1023
c_prog_full_thresh_assert_val_wdch=1023 c_prog_full_thresh_assert_val_wrch=1023 c_prog_full_thresh_negate_val=504 c_prog_full_type=0
c_prog_full_type_axis=0 c_prog_full_type_rach=0 c_prog_full_type_rdch=0 c_prog_full_type_wach=0
c_prog_full_type_wdch=0 c_prog_full_type_wrch=0 c_rach_type=0 c_rd_data_count_width=9
c_rd_depth=512 c_rd_freq=150 c_rd_pntr_width=9 c_rdch_type=0
c_reg_slice_mode_axis=0 c_reg_slice_mode_rach=0 c_reg_slice_mode_rdch=0 c_reg_slice_mode_wach=0
c_reg_slice_mode_wdch=0 c_reg_slice_mode_wrch=0 c_select_xpm=0 c_synchronizer_stage=2
c_underflow_low=0 c_use_common_overflow=0 c_use_common_underflow=0 c_use_default_settings=0
c_use_dout_rst=0 c_use_ecc=0 c_use_ecc_axis=0 c_use_ecc_rach=0
c_use_ecc_rdch=0 c_use_ecc_wach=0 c_use_ecc_wdch=0 c_use_ecc_wrch=0
c_use_embedded_reg=0 c_use_fifo16_flags=0 c_use_fwft_data_count=0 c_use_pipeline_reg=0
c_valid_low=0 c_wach_type=0 c_wdch_type=0 c_wr_ack_low=0
c_wr_data_count_width=9 c_wr_depth=512 c_wr_depth_axis=1024 c_wr_depth_rach=16
c_wr_depth_rdch=1024 c_wr_depth_wach=16 c_wr_depth_wdch=1024 c_wr_depth_wrch=16
c_wr_freq=150 c_wr_pntr_width=9 c_wr_pntr_width_axis=10 c_wr_pntr_width_rach=4
c_wr_pntr_width_rdch=10 c_wr_pntr_width_wach=4 c_wr_pntr_width_wdch=10 c_wr_pntr_width_wrch=4
c_wr_response_latency=1 c_wrch_type=0 core_container=true iptotal=1
x_ipcorerevision=3 x_iplanguage=VHDL x_iplibrary=ip x_ipname=fifo_generator
x_ipproduct=Vivado 2016.4 x_ipsimlanguage=VHDL x_ipvendor=xilinx.com x_ipversion=13.1

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-ruledecks=default::[not_specified] -upgrade_cw=default::[not_specified]
results
cfgbvs-1=1

report_methodology
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
results
timing-18=22 timing-2=1 timing-27=1 timing-4=2

report_power
command_line_options
-advisory=default::[not_specified] -append=default::[not_specified] -file=[specified] -format=default::text
-hier=default::power -l=default::[not_specified] -name=default::[not_specified] -no_propagation=default::[not_specified]
-return_string=default::[not_specified] -rpx=[specified] -verbose=default::[not_specified] -vid=default::[not_specified]
-xpe=default::[not_specified]
usage
airflow=250 (LFM) ambient_temp=25.0 (C) bi-dir_toggle=12.500000 bidir_output_enable=1.000000
board_layers=12to15 (12 to 15 Layers) board_selection=medium (10"x10") bram=0.005042 clocks=0.019521
confidence_level_clock_activity=High confidence_level_design_state=High confidence_level_device_models=High confidence_level_internal_activity=Medium
confidence_level_io_activity=Low confidence_level_overall=Low customer=TBD customer_class=TBD
devstatic=0.158287 die=xc7a200tsbg484-1 dsp_output_toggle=12.500000 dynamic=0.271331
effective_thetaja=3.3 enable_probability=0.990000 family=artix7 ff_toggle=12.500000
flow_state=routed heatsink=medium (Medium Profile) i/o=0.049103 input_toggle=12.500000
junction_temp=26.4 (C) logic=0.003246 mgtavcc_dynamic_current=0.000000 mgtavcc_static_current=0.000000
mgtavcc_total_current=0.000000 mgtavcc_voltage=1.000000 mgtavtt_dynamic_current=0.000000 mgtavtt_static_current=0.000000
mgtavtt_total_current=0.000000 mgtavtt_voltage=1.200000 mmcm=0.191130 netlist_net_matched=NA
off-chip_power=0.000000 on-chip_power=0.429618 output_enable=1.000000 output_load=5.000000
output_toggle=12.500000 package=sbg484 pct_clock_constrained=3.000000 pct_inputs_defined=20
platform=nt64 process=typical ram_enable=50.000000 ram_write=50.000000
read_saif=False set/reset_probability=0.000000 signal_rate=False signals=0.003289
simulation_file=None speedgrade=-1 static_prob=False temp_grade=commercial
thetajb=5.0 (C/W) thetasa=4.6 (C/W) toggle_rate=False user_board_temp=25.0 (C)
user_effective_thetaja=3.3 user_junc_temp=26.4 (C) user_thetajb=5.0 (C/W) user_thetasa=4.6 (C/W)
vccadc_dynamic_current=0.000000 vccadc_static_current=0.020000 vccadc_total_current=0.020000 vccadc_voltage=1.800000
vccaux_dynamic_current=0.112881 vccaux_io_dynamic_current=0.000000 vccaux_io_static_current=0.000000 vccaux_io_total_current=0.000000
vccaux_io_voltage=1.800000 vccaux_static_current=0.030616 vccaux_total_current=0.143497 vccaux_voltage=1.800000
vccbram_dynamic_current=0.000364 vccbram_static_current=0.000764 vccbram_total_current=0.001128 vccbram_voltage=1.000000
vccint_dynamic_current=0.042210 vccint_static_current=0.031414 vccint_total_current=0.073625 vccint_voltage=1.000000
vcco12_dynamic_current=0.000000 vcco12_static_current=0.005000 vcco12_total_current=0.005000 vcco12_voltage=1.200000
vcco135_dynamic_current=0.000000 vcco135_static_current=0.000000 vcco135_total_current=0.000000 vcco135_voltage=1.350000
vcco15_dynamic_current=0.000000 vcco15_static_current=0.000000 vcco15_total_current=0.000000 vcco15_voltage=1.500000
vcco18_dynamic_current=0.000000 vcco18_static_current=0.000000 vcco18_total_current=0.000000 vcco18_voltage=1.800000
vcco25_dynamic_current=0.000000 vcco25_static_current=0.005000 vcco25_total_current=0.005000 vcco25_voltage=2.500000
vcco33_dynamic_current=0.007749 vcco33_static_current=0.005000 vcco33_total_current=0.012749 vcco33_voltage=3.300000
version=2016.4

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_used=7 bufgctrl_util_percentage=21.88
bufhce_available=120 bufhce_fixed=0 bufhce_used=0 bufhce_util_percentage=0.00
bufio_available=40 bufio_fixed=0 bufio_used=0 bufio_util_percentage=0.00
bufmrce_available=20 bufmrce_fixed=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=40 bufr_fixed=0 bufr_used=0 bufr_util_percentage=0.00
mmcme2_adv_available=10 mmcme2_adv_fixed=0 mmcme2_adv_used=2 mmcme2_adv_util_percentage=20.00
plle2_adv_available=10 plle2_adv_fixed=0 plle2_adv_used=0 plle2_adv_util_percentage=0.00
dsp
dsps_available=740 dsps_fixed=0 dsps_used=0 dsps_util_percentage=0.00
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=0 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=1 lvcmos15=0
lvcmos18=0 lvcmos25=1 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=0 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=1
memory
block_ram_tile_available=365 block_ram_tile_fixed=0 block_ram_tile_used=0.5 block_ram_tile_util_percentage=0.14
fifo18e1_only_used=1 ramb18_available=730 ramb18_fixed=0 ramb18_used=1
ramb18_util_percentage=0.14 ramb36_fifo_available=365 ramb36_fifo_fixed=0 ramb36_fifo_used=0
ramb36_fifo_util_percentage=0.00
primitives
bufg_functional_category=Clock bufg_used=7 carry4_functional_category=CarryLogic carry4_used=36
fdce_functional_category=Flop & Latch fdce_used=51 fdpe_functional_category=Flop & Latch fdpe_used=3
fdre_functional_category=Flop & Latch fdre_used=449 fdse_functional_category=Flop & Latch fdse_used=3
fifo18e1_functional_category=Block Memory fifo18e1_used=1 ibuf_functional_category=IO ibuf_used=6
ibufds_functional_category=IO ibufds_used=4 iserdese2_functional_category=IO iserdese2_used=6
lut1_functional_category=LUT lut1_used=23 lut2_functional_category=LUT lut2_used=78
lut3_functional_category=LUT lut3_used=89 lut4_functional_category=LUT lut4_used=71
lut5_functional_category=LUT lut5_used=78 lut6_functional_category=LUT lut6_used=268
mmcme2_adv_functional_category=Clock mmcme2_adv_used=2 muxf7_functional_category=MuxFx muxf7_used=36
muxf8_functional_category=MuxFx muxf8_used=2 obuf_functional_category=IO obuf_used=11
obufds_functional_category=IO obufds_used=4 obuft_functional_category=IO obuft_used=1
oserdese2_functional_category=IO oserdese2_used=6 srl16e_functional_category=Distributed Memory srl16e_used=2
slice_logic
f7_muxes_available=66900 f7_muxes_fixed=0 f7_muxes_used=36 f7_muxes_util_percentage=0.05
f8_muxes_available=33450 f8_muxes_fixed=0 f8_muxes_used=2 f8_muxes_util_percentage=<0.01
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=0 lut_as_logic_available=133800 lut_as_logic_fixed=0
lut_as_logic_used=503 lut_as_logic_util_percentage=0.38 lut_as_memory_available=46200 lut_as_memory_fixed=0
lut_as_memory_used=2 lut_as_memory_util_percentage=<0.01 lut_as_shift_register_fixed=0 lut_as_shift_register_used=2
register_as_flip_flop_available=267600 register_as_flip_flop_fixed=0 register_as_flip_flop_used=506 register_as_flip_flop_util_percentage=0.19
register_as_latch_available=267600 register_as_latch_fixed=0 register_as_latch_used=0 register_as_latch_util_percentage=0.00
slice_luts_available=133800 slice_luts_fixed=0 slice_luts_used=505 slice_luts_util_percentage=0.38
slice_registers_available=267600 slice_registers_fixed=0 slice_registers_used=506 slice_registers_util_percentage=0.19
fully_used_lut_ff_pairs_fixed=0.19 fully_used_lut_ff_pairs_used=51 lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=0
lut_as_logic_available=133800 lut_as_logic_fixed=0 lut_as_logic_used=503 lut_as_logic_util_percentage=0.38
lut_as_memory_available=46200 lut_as_memory_fixed=0 lut_as_memory_used=2 lut_as_memory_util_percentage=<0.01
lut_as_shift_register_fixed=0 lut_as_shift_register_used=2 lut_ff_pairs_with_one_unused_flip_flop_fixed=2 lut_ff_pairs_with_one_unused_flip_flop_used=152
lut_ff_pairs_with_one_unused_lut_output_fixed=152 lut_ff_pairs_with_one_unused_lut_output_used=179 lut_flip_flop_pairs_available=133800 lut_flip_flop_pairs_fixed=0
lut_flip_flop_pairs_used=250 lut_flip_flop_pairs_util_percentage=0.19 slice_available=33450 slice_fixed=0
slice_used=178 slice_util_percentage=0.53 slicel_fixed=0 slicel_used=121
slicem_fixed=0 slicem_used=57 unique_control_sets_used=18 using_o5_and_o6_fixed=18
using_o5_and_o6_used=0 using_o5_output_only_fixed=0 using_o5_output_only_used=2 using_o6_output_only_fixed=2
using_o6_output_only_used=0
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=0 bscane2_util_percentage=0.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
pcie_2_1_available=1 pcie_2_1_fixed=0 pcie_2_1_used=0 pcie_2_1_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=0 xadc_used=0 xadc_util_percentage=0.00

router
usage
actual_expansions=2396967 bogomips=0 bram18=1 bram36=0
bufg=0 bufr=0 congestion_level=0 ctrls=18
dsp=0 effort=2 estimated_expansions=583950 ff=506
global_clocks=7 high_fanout_nets=0 iob=33 lut=557
movable_instances=1286 nets=1486 pins=7382 pll=0
router_runtime=1.000000 router_timing_driven=1 threads=2 timing_constraints_exist=1

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -directive=default::default -fanout_limit=default::10000 -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified] -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] -max_bram=default::-1 -max_bram_cascade_height=default::-1 -max_dsp=default::-1
-max_uram=default::-1 -max_uram_cascade_height=default::-1 -mode=default::default -name=default::[not_specified]
-no_lc=default::[not_specified] -no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified] -part=xc7a200tsbg484-1
-resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] -seu_protect=default::none -shreg_min_size=default::3 -top=top_mod
-verilog_define=default::[not_specified]
usage
elapsed=00:00:36s hls_ip=0 memory_gain=457.336MB memory_peak=666.977MB