module main1(clk,sw,out,data0,data1,data2,data3,data4,data5,data6,data7);
input clk;
wire[0:2] rt0;
wire[0:2] rt1;
wire[0:2] rt2;
wire[0:2] rt3;
wire[0:2] rt4;
wire[0:2] rt5;
wire[0:2] rt6;
wire[0:2] rt7; //rank table
reg [6:0]mem[0:7];
input[0:2] sw;
input [3:0] data0,data1,data2,data3,data4,data5,data6,data7;
always @( clk)
Begin
mem[0][6:3] <=data0; 
mem[1][6:3] <=data1 ; 
mem[2][6:3] <=data2 ; 
mem[3][6:3] <=data3; 
mem[4][6:3] <=data4 ; 
mem[5][6:3] <=data5 ; 
mem[6][6:3] <=data6; 
mem[7][6:3] <=data7 ; 
end 
initial 
begin 
mem[0][2:0] =3'b000; 
mem[1][2:0] =3'b000; 
mem[2][2:0] =3'b000; 
mem[3][2:0] =3'b000; 
mem[4][2:0] =3'b000; 
mem[5][2:0] =3'b000; 
mem[6][2:0] =3'b000; 
mem[7][2:0] =3'b000; 
end 

output [0:2] out; 
wire cmp01 ; // comparator output between 0 and 1// 
comparator c01(mem[0][6:3],mem[1][6:3],cmp01); 
wire cmp02 ; 
comparator c02(mem[0][6:3],mem[2][6:3],cmp02); 
wire cmp03; 
comparator c03(mem[0][6:3],mem[3][6:3],cmp03); 
wire cmp04 ; 
comparator c04(mem[4][6:3],mem[4][6:3],cmp04); 
wire cmp05 ; 
comparator c05(mem[0][6:3],mem[5][6:3],cmp05); 
wire cmp06; 
comparator c06(mem[0][6:3],mem[6][6:3],cmp06); 
wire cmp07 ; 
comparator c07(mem[0][6:3],mem[7][6:3],cmp07); 
wire cmp12 ; 
comparator c12(mem[1][6:3],mem[2][6:3],cmp12); 
wire cmp13 ; 
comparator c13(mem[1][6:3],mem[3][6:3],cmp13); 
wire cmp14 ; 
comparator c14(mem[1][6:3],mem[4][6:3],cmp14); 
wire cmp15 ; 
comparator c15(mem[1][6:3],mem[5][6:3],cmp15); 
wire cmp16 ; 
comparator c16(mem[1][6:3],mem[6][6:3],cmp16); 
wire cmp17 ; 
comparator c17(mem[1][6:3],mem[7][6:3],cmp17);
wire cmp23 ; 
comparator c23(mem[2][6:3],mem[3][6:3],cmp23); 
wire cmp24; 
comparator c24(mem[2][6:3],mem[4][6:3],cmp24); 
wire cmp25 ; 
comparator c25(mem[2][6:3],mem[5][6:3],cmp25); 
wire cmp26 ; 
comparator c26(mem[2][6:3],mem[6][6:3],cmp26); 
wire cmp27 ; 
comparator c27(mem[2][6:3],mem[7][6:3],cmp27); 
wire cmp34 ; 
comparator c34(mem[3][6:3],mem[4][6:3],cmp34); 
wire cmp35 ; 
comparator c35(mem[3][6:3],mem[5][6:3],cmp35); 
wire cmp36 ; 
comparator c36(mem[3][6:3],mem[6][6:3],cmp36); 
wire cmp37 ; 
comparator c37(mem[3][6:3],mem[7][6:3],cmp37); 
wire cmp45 ; 
comparator c45(mem[4][6:3],mem[5][6:3],cmp45); 
wire cmp46 ; 
comparator c46(mem[4][6:3],mem[6][6:3],cmp46); 
wire cmp47 ; 
comparator c47(mem[4][6:3],mem[7][6:3],cmp47); 
wire cmp56 ; 
comparator c56(mem[5][6:3],mem[6][6:3],cmp56); 
wire cmp57 ;  
comparator c57(mem[5][6:3],mem[7][6:3],cmp57);
wire cmp67 ;
comparator c67(mem[6][6:3],mem[7][6:3],cmp67);
// logic modules to compute the rank of each register
rankcal r0(cmp01,cmp02,cmp03,cmp04,cmp05,cmp06,cmp07,rt0[0:2]);
rankcal r1(~cmp01,cmp12,cmp13,cmp14,cmp15,cmp16,cmp17,rt1[0:2]);
rankcal r2(~cmp02,~cmp12,cmp23,cmp24,cmp25,cmp26,cmp27,rt2[0:2]);
rankcal r3(~cmp03,~cmp13,~cmp23,cmp34,cmp35,cmp36,cmp37,rt3[0:2]);
rankcal r4(~cmp04,~cmp14,~cmp24,~cmp34,cmp45,cmp46,cmp47,rt4[0:2]);
rankcal r5(~cmp05,~cmp15,~cmp25,~cmp35,~cmp45,cmp56,cmp57,rt5[0:2]);
rankcal r6(~cmp06,~cmp16,~cmp26,~cmp36,~cmp46,~cmp56,cmp67,rt6[0:2]);
rankcal r7(~cmp07,~cmp17,~cmp27,~cmp37,~cmp47,~cmp57,~cmp67,rt7[0:2]);
mux m1(sw,rt0,rt1,rt2,rt3,rt4,rt5,rt6,rt7,out);
initial
begin
#5 mem[0][2:0] <=rt0;
mem[1][2:0] <=rt1;
mem[2][2:0] <=rt2;
mem[3][2:0] <=rt3;
mem[4][2:0] <=rt4;
mem[5][2:0] <=rt5;
mem[6][2:0] <=rt6;
mem[7][2:0] <=rt7;
end
endmodule