--Engineers : Summer Rutherford, Regita Soetandar --Description: submodule for CLKDivide for ClkFinalDisplay, ButtonClk, SlowClk library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity CLKDivide is Port ( CLKIn : in STD_LOGIC; D90 : in STD_LOGIC_VECTOR (31 downto 0); -- D10 : in STD_LOGIC_VECTOR (31 downto 0); CLKOut : out STD_LOGIC); end CLKDivide; architecture Behavioral of CLKDivide is signal T : std_logic := '0'; begin Divide : process (CLKIn)is variable count : unsigned(31 downto 0) := x"00000000"; begin if rising_edge(CLKIn) then if (std_logic_vector(count) = D90) then count := x"00000000"; T <= not T; else count := count + 1; end if; end if; CLKOut <= T; end process Divide; end Behavioral;