| Device Utilization Summary | [-] |
| Slice Logic Utilization | Used | Available | Utilization | Note(s) |
| Number of Slice Registers |
26 |
126,800 |
1% |
|
| Number used as Flip Flops |
26 |
|
|
|
| Number used as Latches |
0 |
|
|
|
| Number used as Latch-thrus |
0 |
|
|
|
| Number used as AND/OR logics |
0 |
|
|
|
| Number of Slice LUTs |
59 |
63,400 |
1% |
|
| Number used as logic |
59 |
63,400 |
1% |
|
| Number using O6 output only |
53 |
|
|
|
| Number using O5 output only |
0 |
|
|
|
| Number using O5 and O6 |
6 |
|
|
|
| Number used as ROM |
0 |
|
|
|
| Number used as Memory |
0 |
19,000 |
0% |
|
| Number used exclusively as route-thrus |
0 |
|
|
|
| Number of occupied Slices |
26 |
15,850 |
1% |
|
| Number of LUT Flip Flop pairs used |
61 |
|
|
|
| Number with an unused Flip Flop |
35 |
61 |
57% |
|
| Number with an unused LUT |
2 |
61 |
3% |
|
| Number of fully used LUT-FF pairs |
24 |
61 |
39% |
|
| Number of unique control sets |
5 |
|
|
|
Number of slice register sites lost
to control set restrictions |
30 |
126,800 |
1% |
|
| Number of bonded IOBs |
16 |
210 |
7% |
|
| Number of LOCed IOBs |
16 |
16 |
100% |
|
| Number of RAMB36E1/FIFO36E1s |
0 |
135 |
0% |
|
| Number of RAMB18E1/FIFO18E1s |
0 |
270 |
0% |
|
| Number of BUFG/BUFGCTRLs |
2 |
32 |
6% |
|
| Number used as BUFGs |
2 |
|
|
|
| Number used as BUFGCTRLs |
0 |
|
|
|
| Number of IDELAYE2/IDELAYE2_FINEDELAYs |
0 |
300 |
0% |
|
| Number of ILOGICE2/ILOGICE3/ISERDESE2s |
0 |
300 |
0% |
|
| Number of ODELAYE2/ODELAYE2_FINEDELAYs |
0 |
|
|
|
| Number of OLOGICE2/OLOGICE3/OSERDESE2s |
0 |
300 |
0% |
|
| Number of PHASER_IN/PHASER_IN_PHYs |
0 |
24 |
0% |
|
| Number of PHASER_OUT/PHASER_OUT_PHYs |
0 |
24 |
0% |
|
| Number of BSCANs |
0 |
4 |
0% |
|
| Number of BUFHCEs |
0 |
96 |
0% |
|
| Number of BUFRs |
0 |
24 |
0% |
|
| Number of CAPTUREs |
0 |
1 |
0% |
|
| Number of DNA_PORTs |
0 |
1 |
0% |
|
| Number of DSP48E1s |
0 |
240 |
0% |
|
| Number of EFUSE_USRs |
0 |
1 |
0% |
|
| Number of FRAME_ECCs |
0 |
1 |
0% |
|
| Number of IBUFDS_GTE2s |
0 |
4 |
0% |
|
| Number of ICAPs |
0 |
2 |
0% |
|
| Number of IDELAYCTRLs |
0 |
6 |
0% |
|
| Number of IN_FIFOs |
0 |
24 |
0% |
|
| Number of MMCME2_ADVs |
0 |
6 |
0% |
|
| Number of OUT_FIFOs |
0 |
24 |
0% |
|
| Number of PCIE_2_1s |
0 |
1 |
0% |
|
| Number of PHASER_REFs |
0 |
6 |
0% |
|
| Number of PHY_CONTROLs |
0 |
6 |
0% |
|
| Number of PLLE2_ADVs |
0 |
6 |
0% |
|
| Number of STARTUPs |
0 |
1 |
0% |
|
| Number of XADCs |
0 |
1 |
0% |
|
| Average Fanout of Non-Clock Nets |
4.04 |
|
|
|