| mod_VGA Project Status (05/07/2014 - 18:57:20) | |||
| Project File: | OV7670.xise | Parser Errors: | No Errors |
| Module Name: | mod_Image | Implementation State: | Programming File Not Generated |
| Target Device: | xc7a100t-1csg324 |
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| Product Version: | ISE 14.5 |
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| Design Goal: | Balanced |
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| Design Strategy: | Xilinx Default (unlocked) |
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| Environment: | System Settings |
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| Device Utilization Summary (estimated values) | [-] | |||
| Logic Utilization | Used | Available | Utilization | |
| Number of bonded IOBs | 0 | 210 | 0% | |
| Detailed Reports | [-] | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos | |
| Synthesis Report | Current | mi. 7. may. 16:43:23 2014 | ||||
| Translation Report | ||||||
| Map Report | ||||||
| Place and Route Report | ||||||
| CPLD Fitter Report (Text) | ||||||
| Power Report | ||||||
| Post-PAR Static Timing Report | ||||||
| Bitgen Report | ||||||
| Secondary Reports | [-] | ||
| Report Name | Status | Generated | |
| WebTalk Report | Out of Date | mi. 7. may. 18:57:11 2014 | |
| WebTalk Log File | Out of Date | mi. 7. may. 18:57:20 2014 | |