mod_VGA Project Status (05/07/2014 - 18:57:20)
Project File: | OV7670.xise | Parser Errors: | No Errors
Module Name: | mod_Image | Implementation State: | Programming File Not Generated
Target Device: | xc7a100t-1csg324 | Errors: |
Product Version: | ISE 14.5 | Warnings: |
Design Goal: | Balanced | Routing Results: |
Design Strategy: | Xilinx Default (unlocked) | Timing Constraints: |
Environment: | System Settings | Final Timing Score: |

Device Utilization Summary (estimated values) | [-]
Logic Utilization | Used | Available | Utilization
Number of bonded IOBs | 0 | 210 | 0%

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report | Current | mi. 7. may. 16:43:23 2014 |  |  |
Translation Report |  |  |  |  |
Map Report |  |  |  |  |
Place and Route Report |  |  |  |  |
CPLD Fitter Report (Text) |  |  |  |  |
Power Report |  |  |  |  |
Post-PAR Static Timing Report |  |  |  |  |
Bitgen Report |  |  |  |  |

Secondary Reports | [-]
Report Name | Status | Generated
WebTalk Report | Out of Date | mi. 7. may. 18:57:11 2014
WebTalk Log File | Out of Date | mi. 7. may. 18:57:20 2014

Date Generated: 05/07/2014 - 19:01:40