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-- Company: 
-- Engineer: 
-- 
-- Create Date: 12/02/2016 08:58:01 AM
-- Design Name: 
-- Module Name: clk_div - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity clk_div is
    Port ( clk : in STD_LOGIC;
           divisor : in STD_LOGIC_VECTOR (31 downto 0);
           clk_out : out STD_LOGIC);
end clk_div;

architecture Behavioral of clk_div is
    signal clk_toggle : std_logic := '0';

begin

    process (clk) is
    variable count : unsigned (31 downto 0) := x"00000000";
    begin
        if (count = unsigned(divisor)) then
            count := x"00000000";
            clk_toggle <= NOT clk_toggle;
        elsif (rising_edge(clk)) then
            count := count + 1;
        end if;
    end process;

    clk_out <= clk_toggle;









end Behavioral;