---------------------------------------------------------------------------------- -- Company: Cal Poly EE Department -- Engineer: Riley Olson, Dan Potts, Bill Blakely -- -- Create Date: 11/20/2015 09:17:12 AM -- Design Name: -- Module Name: PWM - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: This module takes a 7-bit input DUTY, and generates a pulse width modulated signal with a duty cycle of DUTY / 128 -- -- Dependencies: None -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; -- entity PWM is Port ( DUTY : in STD_LOGIC_VECTOR(6 downto 0); CLK : in STD_LOGIC; PWM: out STD_LOGIC); end PWM; --The behavioral setup is very similar to a clock-divider architecture Behavioral of PWM is constant max_cnt : integer := 128; begin thing : process(DUTY, CLK) variable count : integer := 0; variable dty : integer := 0; begin if(rising_edge(CLK)) then dty := to_integer(unsigned(DUTY)); if(count >= max_cnt) then--resets the count after one period count := 0; end if; if(count < dty) then--determines if the PWM signal should be low or high based on the DUTY input PWM <= '1'; else PWM <= '0'; end if; count := count + 1;--increments count end if; end process; end Behavioral;