---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 06/04/2018 02:25:23 PM -- Design Name: -- Module Name: topLeval - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity topLeval is Port ( clk : in std_logic ; led : out std_logic_vector(4 downto 0); btn : in std_logic; an : out std_logic_vector(3 downto 0); seg : out std_logic_vector(7 downto 0)); end topLeval; architecture Behavioral of topLeval is component gameLogic is Port ( boardSIn : in std_logic; btn : in std_logic; score : out std_logic_vector(7 downto 0); clk : in std_logic); end component; component sseg_dec is Port ( ALU_VAL : in std_logic_vector(7 downto 0); SIGN : in std_logic; VALID : in std_logic; CLK : in std_logic; DISP_EN : out std_logic_vector(3 downto 0); SEGMENTS : out std_logic_vector(7 downto 0)); end component; --component lab5 is --Port ( --BTN2 : in STD_LOGIC; --BTN3: in STD_LOGIC; --ENABLE : in STD_LOGIC; --BTN0 : in STD_LOGIC; -- SEG : out STD_LOGIC_VECTOR(3 downto 0); -- SW : in STD_LOGIC_VECTOR(3 downto 0); --C : out STD_LOGIC_VECTOR(7 downto 0)); -- end component; component clk_div2 is Port ( clk : in std_logic; sclk : out std_logic); end component; component positionSM is Port ( clk1 : in STD_LOGIC; leds : out STD_LOGIC_VECTOR(4 downto 0); boardState : out STD_LOGIC); end component; component debounce is -- Debounced button with a 20 ms debounce time. generic( clk_period : time := 20 ns; -- clock period debounce_time : time := 20 ms; -- time after which the signal is considered stable on_state : std_logic := '1' -- pushed state (vs rest state) ); port( input : IN std_logic; output : OUT std_logic; clk : IN std_logic ); end component; signal inClk : std_logic; signal inBS : std_logic; signal inScore : std_logic_vector(7 downto 0); signal inIn : std_logic; begin clockD : clk_div2 port map ( clk => clk, sclk => inClk); psm : positionSM port map ( clk1 => inClk, leds => led, boardState => inBS); gLog : gameLogic port map ( boardSIn => inBS, btn => btn, score => inScore, clk => inclk); -- sseg2 : lab5 -- port map ( SW => inScore, -- SEG => an, -- C => seg); db : debounce port map( input => btn, output => inIn, clk => clk); sseg : sseg_dec port map ( alu_val => inScore, clk => clk, disp_en => an, segments => seg, sign => '0', valid => '1'); end Behavioral;