----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    00:00:42 12/02/2014 
-- Design Name: 
-- Module Name:    score8adder - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity score8adder is
    Port ( hits : in  STD_LOGIC_vector (7 downto 0);
				valids : in std_logic_vector(7 downto 0);
				clk : in std_logic;
				reset : in std_logic;
				finalscore : out std_logic_vector(7 downto 0);
				succ : out std_logic_vector (7 downto 0);
				endgame : out std_logic
	 );
end score8adder;

architecture Behavioral of score8adder is

signal currentscore1: std_logic_vector(7 downto 0):= "00000000";
signal currentscore2: std_logic_vector(7 downto 0):= "00000000";
signal currentscore3: std_logic_vector(7 downto 0):= "00000000";
signal currentscore4: std_logic_vector(7 downto 0):= "00000000";
signal currentscore5: std_logic_vector(7 downto 0):= "00000000";
signal currentscore6: std_logic_vector(7 downto 0):= "00000000";
signal currentscore7: std_logic_vector(7 downto 0):= "00000000";
signal currentscore8: std_logic_vector(7 downto 0):= "00000000";
signal newscore1 : std_logic_vector(7 downto 0) := "00000000";
signal newscore2 : std_logic_vector(7 downto 0) := "00000000";
signal newscore3 : std_logic_vector(7 downto 0) := "00000000";
signal newscore4 : std_logic_vector(7 downto 0) := "00000000";
signal newscore5 : std_logic_vector(7 downto 0) := "00000000";
signal newscore6 : std_logic_vector(7 downto 0) := "00000000";
signal newscore7 : std_logic_vector(7 downto 0) := "00000000";
signal newscore8 : std_logic_vector(7 downto 0) := "00000000";
signal endgame1 : std_logic_vector (0 downto 0) := "0";
signal endgame2 : std_logic_vector (0 downto 0) := "0";
signal endgame3 : std_logic_vector (0 downto 0) := "0";
signal endgame4 : std_logic_vector (0 downto 0) := "0";
signal endgame5 : std_logic_vector (0 downto 0) := "0";
signal endgame6 : std_logic_vector (0 downto 0) := "0";
signal endgame7 : std_logic_vector (0 downto 0) := "0";
signal endgame8 : std_logic_vector (0 downto 0) := "0";
signal endgame9 : std_logic_vector (0 downto 0) := "0";
signal hits1 : std_logic_vector(7 downto 0):= "00000000";
signal hits2 : std_logic_vector(7 downto 0):= "00000000";
signal hits3 : std_logic_vector(7 downto 0):= "00000000";
signal hits4 : std_logic_vector(7 downto 0):= "00000000";
signal hits5 : std_logic_vector(7 downto 0):= "00000000";
signal hits6 : std_logic_vector(7 downto 0):= "00000000";
signal hits7 : std_logic_vector(7 downto 0):= "00000000";
signal hits8 : std_logic_vector(7 downto 0):= "00000000";
signal suc : std_logic_vector(7 downto 0) := "00000000";
signal success1 : std_logic;

component ripplecarryadder is
Port ( A : in  STD_LOGIC_VECTOR (7 downto 0);
           B : in  STD_LOGIC_VECTOR (7 downto 0);
			  Enable : in std_logic;
			  reset : in std_logic;
           Sum : out  STD_LOGIC_VECTOR (7 downto 0);
           Carryout : out  STD_LOGIC_VECTOR (0 downto 0);
			  success : out std_logic);
end component RippleCarryAdder;


component add8scores is
port (score1 : in  STD_LOGIC_vector (7 downto 0);
				score2 : in  STD_LOGIC_vector (7 downto 0);
				score3 : in  STD_LOGIC_vector (7 downto 0);
				score4 : in  STD_LOGIC_vector (7 downto 0);
				score5 : in  STD_LOGIC_vector (7 downto 0);
				score6 : in  STD_LOGIC_vector (7 downto 0);
				score7 : in  STD_LOGIC_vector (7 downto 0);
				score8 : in  STD_LOGIC_vector (7 downto 0);
				reset : in std_logic;
				max : out std_logic_vector (0 downto 0);
				success1 : out std_logic;
				addedscore : out  STD_LOGIC_vector (7 downto 0)
		);
end component add8scores;

component dflip is
    Port ( D : in std_logic;
				nxtstate: in  STD_LOGIC_vector(7 downto 0);
				clk : in std_logic;
				Q : out std_logic_vector(7 downto 0)
				);
end component dflip;




begin

process (hits)
begin
hits1 <= "00000000";
hits2 <= "00000000";
hits3 <= "00000000";
hits4 <= "00000000";
hits5 <= "00000000";
hits6 <= "00000000";
hits7 <= "00000000";
hits8 <= "00000000";
hits1(0) <= hits(0);
hits2(0) <= hits(1);
hits3(0) <= hits(2);
hits4(0) <= hits(3);
hits5(0) <= hits(4);
hits6(0) <= hits(5);
hits7(0) <= hits(6);
hits8(0) <= hits(7);
end process;	
					

scoreadd1: ripplecarryadder port map ( A => currentscore1,
													B => hits1,
													enable => valids(0),
													reset => reset,
													sum => newscore1,
													carryout => endgame1,
													success => suc(0));
													
scoreadd2: ripplecarryadder port map ( A => currentscore2,
													B => hits2,
													enable => valids(1),
													reset => reset,
													sum => newscore2,
													carryout => endgame2,
													success => suc(1));
													
scoreadd3: ripplecarryadder port map ( A => currentscore3,
													B => hits3,
													enable => valids(2),
													reset => reset,
													sum => newscore3,
													carryout => endgame3,
													success => suc(2));	
													
scoreadd4: ripplecarryadder port map ( A => currentscore4,
													B => hits4,
													enable => valids(3),
													reset => reset,
													sum => newscore4,
													carryout => endgame4,
													success => suc(3));
													
scoreadd5: ripplecarryadder port map ( A => currentscore5,
													B => hits5,
													enable => valids(4),
													reset => reset,
													sum => newscore5,
													carryout => endgame5,
													success => suc(4));
													
scoreadd6: ripplecarryadder port map ( A => currentscore6,
													B => hits6,
													enable => valids(5),
													reset => reset,
													sum => newscore6,
													carryout => endgame6,
													success => suc(5));
scoreadd7: ripplecarryadder port map ( A => currentscore7,
													B => hits7,
													enable => valids(6),
													reset => reset,
													sum => newscore7,
													carryout => endgame7,
													success => suc(6));
scoreadd8: ripplecarryadder port map ( A => currentscore8,
													B => hits8,
													enable => valids(7),
													reset => reset,
													sum => newscore8,
													carryout => endgame8,
													success => suc(7));

addscores: add8scores port map ( score1 => currentscore1,
											score2 => currentscore2,
											score3 => currentscore3,
											score4 => currentscore4,
											score5 => currentscore5,
											score6 => currentscore6,
											score7 => currentscore7,
											score8 => currentscore8,
											max => endgame9,
											reset => reset,
											success1 => success1,
											addedscore => finalscore);
succ <= suc;





dflip1 : dflip port map (D => suc(0),
								nxtstate => newscore1,
								clk => clk,
								q => currentscore1);
dflip2 : dflip port map (D => suc(1),
								nxtstate => newscore2,
								clk => clk,
								q => currentscore2);
dflip3 : dflip port map (D => suc(2),
								nxtstate => newscore3,
								clk => clk,
								q => currentscore3);
dflip4 : dflip port map (D => suc(3),
								nxtstate => newscore4,
								clk => clk,
								q => currentscore4);
dflip5 : dflip port map (D => suc(4),
								nxtstate => newscore5,
								clk => clk,
								q => currentscore5);
dflip6 : dflip port map (D => suc(5),
								nxtstate => newscore6,
								clk => clk,
								q => currentscore6);
dflip7 : dflip port map (D => suc(6),
								nxtstate => newscore7,
								clk => clk,
								q => currentscore7);
dflip8 : dflip port map (D => suc(7),
								nxtstate => newscore8,
								clk => clk,
								q => currentscore8);

endgame <= endgame1(0) and endgame2(0) and endgame3(0) and endgame4(0) and endgame5(0) and endgame6(0) and endgame7(0) and endgame8(0) and endgame9(0);

end Behavioral;