---------------------------------------------------------------------------------- -- Engineer: Jason Portillo -- -- Module Name: counter - Behavioral ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity counter is Port ( en: in std_logic; rst: in std_logic; Vin: in std_logic_vector (5 downto 0); --Value In : switches LD_EN: in std_logic; -- Button load enable s_clk: in std_logic; CO: out std_logic; -- if count hits 59seconds data: out std_logic_vector (5 downto 0) ); end counter; architecture Behavioral of counter is signal Qout: std_logic_vector (5 downto 0); begin process (en,s_clk,rst,LD_EN,Vin) begin if rst= '1' then Qout <= "000000"; elsif LD_EN = '1' then Qout <= Vin; elsif (rising_edge(s_clk) and en ='1') then if Qout = "111011" then Qout <= "000000" ; CO <= '1'; --to do 60-64 do not let happen else CO <= '0'; Qout <= Qout + 1; end if; else Qout <= Qout; end if; end process; data <= Qout; end Behavioral;