---------------------------------------------------------------------------------- -- Company: Cal Poly EE Department -- Engineer: Riley Olson, Dan Potts, Bill Blakely -- -- Create Date: 12/03/2015 07:44:04 PM -- Design Name: -- Module Name: TEST - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: Master, MUX -- -- Dependencies: Testing block that uses switches and an internal mux to simulate signals from the sensor array and sends them to the Master module. For testing the master block. -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity TEST is Port ( CLK : in STD_LOGIC; SWCH : in STD_LOGIC_VECTOR(11 downto 0);--Switches act as sensor data REF : out STD_LOGIC;--REF PWM to comparator circuit X_OUT : out STD_LOGIC);--PWM output to servo end TEST; architecture Behavioral of TEST is component Master is Port ( CLK : in STD_LOGIC; VAL_IN : in STD_LOGIC_VECTOR(2 downto 0); SEL : out STD_LOGIC_VECTOR(2 downto 0); X_OUT : out STD_LOGIC; REF : out STD_LOGIC); end component; component MUX is Port ( INPUT : in STD_LOGIC_VECTOR(11 downto 0); SEL : STD_LOGIC_VECTOR(2 downto 0); OUTPUT : out STD_LOGIC_VECTOR(2 downto 0)); end component; signal SEL : STD_LOGIC_VECTOR(2 downto 0); signal VAL : STD_LOGIC_VECTOR(2 downto 0); begin --Wiring up the mux and master modules MST : MASTER PORT MAP(CLK => CLK, VAL_IN => VAL, SEL => SEL, X_OUT => X_OUT, REF => REF); MX : MUX PORT MAP(INPUT => SWCH, SEL => SEL, OUTPUT => VAL); end Behavioral;