---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 03/11/2018 07:14:22 PM -- Design Name: -- Module Name: main - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity main is Port ( SENSOR : in STD_LOGIC; ENABLE : in STD_LOGIC; CLOCK : in STD_LOGIC; --LED1: out STD_LOGIC; --LED2: out STD_LOGIC; ANODE : out STD_LOGIC_VECTOR(3 downto 0); CATHODE : out STD_LOGIC_VECTOR(7 downto 0)); end main; architecture Behavioral of main is component ard_dff is Port ( D : in STD_LOGIC; E : in STD_LOGIC; CLK : in STD_LOGIC; Q : out STD_LOGIC); end component; component ard_disp is Port ( DATA : in STD_LOGIC; CLK : in STD_LOGIC; CATHODE : out STD_LOGIC_VECTOR(7 downto 0); ANODE : out STD_LOGIC_VECTOR(3 downto 0)); end component; signal n1 : STD_LOGIC; begin bb0 : ard_dff port map ( D => SENSOR, E => ENABLE, CLK => CLOCK, Q => n1); bb1 : ard_disp port map( DATA => n1, CLK => CLOCK, ANODE => ANODE, CATHODE => CATHODE); end Behavioral;